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YMU757B
-34-
Serial I/F Specifications
The YMU757B is controlled through the three serial interfaces SCLK, SYNC and SDIN.
About the relations between SDIN and SCLK
The value of SDIN is taken in the inside of the LSI at the SCLK rise.
Input SDIN so that setup/Hold time is secured to rise edge of SCLK.
(Refer to the AC characteristics of the electric characteristics for the details of the timing specification.)
About SDIN
The figure above shows no data transmission between Index data and Control data but it means nothing
problematic. 24 bit continuous data transmission is also possible.
When transmitting the data by 8-bit unit, transmit the upper 8 bits and lower 8 bits of the control data separately.
There is no particular specification for the interval between the end of transmission of the upper 8 bits and start of
transmission of the lower 8 bits. However, the longer the interval is, the longer time one transmission takes. When
entering the musical score data into FIFO, use care not to make FIFO empty.
About SYNC
It can correspond to Type1 and Type2 of the upper figure.
When rise edge of SYNC occurs inside the LSI, it considers that the data transfer of one time was completed.
SDIN for 24×SCLK just before rise edge of SYNC occurs is judged valid data.
(SDIN for 16×SCLK are valid data when transfer only Control Data.)
There is no regulation specially about the length of the H period.
But, L period is to make 100ns be secured at least in the case of the Type2 wave shape
It has the possibility that faulty operation is caused when rise edge of SYNC and fall edge of SCLK approach it.
Give careful consideration to rise edge of SCLK doesn’t occur toward rise edge of SYNC.
About the data transfer only Control Data.
If input SDIN for SCLK×16 between rise edge of SYNC and next rise edge of SYNC, the inside of the LSI is
judged it is music data ($00h) and take it.
SCLK
8 clk
16 clk
SYNC
Type1
SDIN
MSB
LSB
MSB
LSB
Index Data (8bit)
Control Data (16bit)
6
7
1 0
15
1 0
MSB
6
7
SYNC
Type2