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參數(shù)資料
| 型號： | YSS901 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Hook-Up Wire; Conductor Size AWG:16; No. Strands x Strand Size:26 x 30; Jacket Color:White; Approval Bodies:UL, CSA; Approval Categories:UL AWM Styles 1007, 1565; CSA Types TR-64, TRSR-64; JQA-F; Passes VW-1 Flame Test RoHS Compliant: Yes |
| 中文描述： | 統(tǒng)計立體聲偶極子 |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 140K |
| 代理商： | YSS901 |
YSS901
3
g Pin Description
No.
Pin name
I/O
Function
5
DVDD
-
Digital signal power supply : +5 V
6
CTLSEL
I
Selection of control method
7
SYNCN
I
Digital input/output synchronization signal
8
BCLK
I
Digital input/output bit clock
9
CSN
I
Serial control interface chip select signal
10
DOUT
O
Digital signal output
11
DIN
I
Digital signal input
12
DSEL2
I
Analog/digital input selection
13
DSEL1
I
Digital input/output format selection
14
DSEL0
I
Digital input/output format selection
15
DVDD
-
Digital signal power supply : +5 V
21
TST2
-
Test (To be open.)
22
DVSS
-
Digital signal ground
23
AVSS
-
Analog signal ground
24
AIRRET
AO
Right channel analog signal input return
25
AIROUT
AO
Right channel analog signal input out
26
AIR
AI
Right channel analog signal input
27
AILRET
AO
Left channel analog signal input return
28
AILOUT
AO
Left channel analog signal input out
29
AIL
AI
Left channel analog signal input
30
VREF
AI
Analog signal VREF
31
AVDD
-
Analog signal power supply : +5 V
37
LOUT
AO
Left channel analog signal output
38
ROUT
AO
Right channel analog signal output
39
PLLC
AI
PLL auxiliary input
40
AVSS
-
Analog signal ground
41
EXTAL
I
Crystal clock input
42
XTAL
O
Crystal clock output
43
DVSS
-
Digital signal ground
44
TSTCK
-
Test (Connect with DVSS.)
45
TST1
-
Test (To be open.)
46
TSTNI
I
Test (Connect with DVSS.)
47
TSTNO
O
Test (To be open.)
53
DVDD
-
Digital signal power supply: +5 V
54
TSTSEL
-
Test (Connect with DVSS.)
55
CSEL2
I
Coefficient selection (Enabled when CTLSEL = 0)
56
CSEL1
I
Coefficient selection (Enabled when CTLSEL = 0)
57
CSEL0
I
Coefficient selection (Enabled when CTLSEL = 0)
58
RESETN
I
Reset signal input
59
BSFT1
I
Bit shift selection (Enabled when CTLSEL = 0)
60
BSFT0
I
Bit shift selection (Enabled when CTLSEL = 0)
61
SCK
I
Serial control interface clock input
62
SI
I
Serial control interface data input
63
DVSS
-
Digital signal ground
Notes:
1. Pins of No. 1 to 4, 16 to 20, 32 to 36, 48 to 52 and 64 are to be open.
2.
I: input pin
O: output pin
AI: analog signal input pin
AO: analog output pin.
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