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參數(shù)資料
| 型號(hào)： | YSS901 |
| 廠商： | Yamaha Corporation |
| 英文描述： | Stereo Dipole System(SD)( 立體聲偶極系統(tǒng)) |
| 中文描述： | 立體聲偶極子系統(tǒng)（特別職務(wù)）（立體聲偶極系統(tǒng)） |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 140K |
| 代理商： | YSS901 |
YSS901
5
g Outline of Functions
1. Clock signals
XTAL, EXTAL
and PLLC
For the clock signal, use the crystal connected to XTAL EXTAL pin with which the clock signal is obtained by the
self-oscillation at the crystal oscillation circuit, or external signal supplied through EXTAL pin. The frequency of the
clock obtained by the self-oscillation is 2.822 MHz (or 44.1 kHz * 64). The internal operation is carried out with 512
fs clock that is made by the PLL.
Insert an analog filter in between PLLC and GND pins.
2. Data input/output signals
Analog/digital input selection pin: DSEL2
This pin is used to select a type of the input signal. DSEL2 = 0 selects the digital signal input, or DSEL2 = 1 selects
the analog signal input.
2-1) Digital signal
Digital signal input/output pins:
DIN, BCLK, SYNCN
and DOUT
Digital signals should be inputted through DIN, BCLK and SYNCN pins.
DIN signal (PCM data) must be in synchronous with BCLK (bit clock) and SYNCN (word clock) signals.
Digital signal is outputted from DOUT pin.
Input/output format designation pins: DSEL1 and DSEL0
These pins are used to designate a data format for DAC. The settings of DSEL1 and DSEL0 and their output formats
are as follows.
DSEL1
DSEL0
DAC output format
00
48 fs
16 bits
Data LSB justified
01
48 fs
18 bits
Data LSB justified (Bits 1 and 0 are “0”.)
10
48 fs
20 bits
Data LSB justified (Bits 3 through 0 are “0”.)
11
64 fs
16 bits
Data MSB justified (Delay by one bit)
For the details of the format, refer to “Serial Data Interface” explained later in this document.
2-2) Analog signal
Analog input/output pins:
AIL, AILOUT, AILRET, LOUT, AIR, AIROUT, AIRRET
and ROUT
Analog signals should be inputted through AIL and AIR pins. The signals that have been processed by the stereo
dipole (SD) are outputted from LOUT and ROUT pins respectively. Add an analog filter circuit, an example of
which is shown later in this document.
Center voltage pin
VREF
This pin outputs a reference voltage for analog signal processing. Connect an appropriate capacitor between VREF
and GND pins.
3. Controlling functions
3-1) Control method selection pin:
CTLSEL
This pin is used for selection of a control method as described below.
CTLSEL = 0 : Selection of CSEL2, CSEL1 or CSEL0 by means of DC switch (H/L) is enabled.
CTLSEL = 1 : Selection of CSN, SI or SCK through the microcomputer is enabled.
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