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參數(shù)資料
| 型號： | YSS920-SZ |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | LEAD FREE, SQFP-100 |
| 文件頁數(shù)： | 19/28頁 |
| 文件大?。?/td> | 881K |
| 代理商： | YSS920-SZ |
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YSS920
26
2) When using multiple YSS920s
An example of the basic connection when multiple YSS920s are used is indicated below:
YSS920
(EVE)
XI
HOST
PROCESSOR
/C
S
SC
K
SI
SO
XO
S
D
BCK
S
D
WC
K
SDO0
SDO2
SDO3
SRAM or DRAM
(option)
12.288～15.000MHz
CP
O
1kΩ
4700p
F
RA
M
D
15
-0
CA
S
N
RA
S
N
RA
M
W
E
N
RA
M
O
E
N
RA
M
A
17
-0
/I
C
470pF
SDO1
SDO4
SDO6
SDO7
SDO5
SDI0
SDI2
SDI3
SDI1
SDI4
SDI6
SDI7
SDI5
64fs
fs
YSS920
(EVE)
XI
/C
S
SC
K
SI
SO
XO
S
D
BCK
S
D
WC
K
SDO0
SDO2
SDO3
SRAM or DRAM
(option)
CP
O
1kΩ
4700pF
RA
M
D
15
-0
CA
S
N
RA
S
N
RA
M
W
E
N
RA
M
O
E
N
RA
M
A
17
-0
/I
C
470pF
SDO1
SDO4
SDO6
SDO7
SDO5
SDI0
SDI2
SDI3
SDI1
SDI4
SDI6
SDI7
SDI5
IO
PO
R
T
15
IO
PO
R
T
14
IO
PO
R
T
13
IO
PO
R
T
12
IO
PO
R
T
15
IO
PO
R
T
14
IO
PO
R
T
13
IO
PO
R
T
12
/IC
/CS can be shared by setting chip addresses (CA3-0) to the IOPORT15-12 pins.
When switching the device to be controlled, rewrite the control register address 0 x 00(CA3-0).
For example, in the case above:
To control the left device, set the register as CAE=1 and CA3-0=0000,
To control the right device, set the register as CAE=1 and CA3-0=0001.
On peripheral devices such as the ADC and DAC that require a bit clock with inversed polarity, use the
SDBCKO output from the IOPORT18 pin by setting IOSEL18=1, OPSEL18=1, and BCKOP=1.
The SO pin may become High-Z. Therefore, pull-up resistors may be necessary on some systems.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| YSS932 | 制造商:YAMAHA 制造商全稱:YAMAHA CORPORATION 功能描述:96kHz DIR + Dolby Digital / Pro Logic II / DTS decoder + Sub DSP |
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| YSS943 | 制造商:YAMAHA 制造商全稱:YAMAHA CORPORATION 功能描述:ADAMB Advanced Digital Audio Multi channel decode processor |
| YSS944 | 制造商:YAMAHA 制造商全稱:YAMAHA CORPORATION 功能描述:ADAMB Advanced Digital Audio Multi channel decode processor |
| YSS950 | 制造商:YAMAHA 制造商全稱:YAMAHA CORPORATION 功能描述:DAP1 Digital Audio Processor |
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