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| 型號(hào)： | Z85233 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | The Zilog SCC Serial Communication Controller |
| 中文描述： | Zilog公司鱗癌的串行通信控制器 |
| 文件頁(yè)數(shù)： | 72/317頁(yè) |
| 文件大?。?/td> | 3201K |
| 代理商： | Z85233 |
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SCC/ESCC User’s Manual
SCC/ESCC Ancillary Support Circuitry
3-11
3
The output of the transmit clock derived from this counter
is available to the /TRxC pin when the DPLL output is
selected as the transmit clock source. Care must be taken
using ESCC in SDLC Loop mode with the DPLL. The
SDLC Loop mode requires synchronized Tx and Rx
clocks, but the ESCC’s DPLL might be off-sync because of
this Transmit Clock Counter. In SDLC Loop, one should
instead echo the signal of the RxDPLL out to clock the
receiver and transmitter to achieve synchronization. This
can be programmed via bits D1-D0 in WR11.
3.5 CLOCK SELECTION
The SCC can select several clock sources for internal and
external use. Write Register 11 is the Clock Mode Control
register for both the receive and transmit clocks. It deter-
mines the type of signal on the /SYNC and /RTxC pins and
the direction of the /TRxC pin.
The SCC is programmed to select one of several sources
to provide the transmit and receive clocks.
The source of the receive clock is controlled by bits D6 and
D5 of WR11. The receive clock may be programmed to
come from the /RTxC pin, the /TRxC pin, the output of the
baud rate generator, or the receive output of the DPLL.
The source of the transmit clock is controlled by bits D4
and D3 of WR11. The transmit clock may be programmed
to come from the /RTxC pin, the /TRxC pin, the output of
the baud rate generator, or the transmit output of the
DPLL.
Ordinarily, the /TRxC pin is an input, but it can become an
output if this pin has not been selected as the source for
the transmitter or the receiver, and bit D2 of WR11 is set
to 1. The selection of the signal provided on the /TRxC out-
put pin is controlled by bits D1 and D0 of WR11. The
/TRxC pin is programmed to provide the output of the crys-
tal oscillator, the output of the baud rate generator, the re-
ceive output of the DPLL or the actual transmit clock. If the
output of the crystal oscillator is selected, but the crystal
oscillator has not been enabled, the /TRxC pin is driven
High. The option of placing the transmit clock signal on the
/TRxC pin when it is an output allows access to the trans-
mit output of the DPLL.
Figure 3-10 shows a simplified schematic diagram of the
circuitry used in the clock multiplexing. It shows the inputs
to the multiplexer section, as well as the various signal in-
versions that occur in the paths to the outputs.
Selection of the clocking options may be done anywhere in
the initialization sequence, but the final values must be se-
lected before the receiver, transmitter, baud rate genera-
tor, or DPLL are enabled to prevent problems from arbi-
trarily narrow clock signals out of the multiplexers. The
same is true of the crystal oscillator, in that the output
should be allowed to stabilize before it is used as a clock
source.
Also shown are the edges used by the receiver, transmit-
ter, baud rate generator and DPLL to sample or send data
or otherwise change state. For example, the receiver sam-
ples data on the falling edge, but since there is an inver-
sion in the clock path between the /RTxC pin and the re-
ceiver, a rising edge of the /RTxC pin samples the data for
the receiver.
The following shows three examples for selecting different
clocking options. Figure 3-11 shows the clock set up for
asynchronous transmission, 16x clock mode using the on-
chip oscillator with an external crystal. This example uses
the oscillator as the input to the baud rate generator, al-
though it can be used directly as the transmit or receive clock
source. The registers involved are WR11 through WR14 and
the figure shows the programming in these registers.
An example of asynchronous communication where a 1x
clock is obtained from an external MODEM is shown in
Figure 3-12. The data encoding is NRZ. Note that:
1.
The BRG is not used under this configuration.
Figure 3-9. DPLL Transmit Clock Counter Output (ESCC only)
DPLL
DPLL Counter
Input Divided by 16 (FM0 or FM1)
Input Divided by 32 for NRZI
DPLL Output to Receiver
DPLL Output to Transmitter
DPLL CLK
Input
UM010901-0601
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