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參數(shù)資料
| 型號(hào)： | Z86108 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | 8 Bit CMOS Low Cost MCU(8位CMOS低成本微控制器（帶2K ROM)) |
| 中文描述： | 8位CMOS低成本微控制器（8位的CMOS低成本微控制器（帶2K光盤）） |
| 文件頁數(shù)： | 19/28頁 |
| 文件大?。?/td> | 394K |
| 代理商： | Z86108 |
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Z86108
ZiLOG
CMOS 8-Bit Low-Cost 2K-ROM Microcontrollers
DS001800-Z8X0898
P R E L I M I N A R Y
19
Clock.
The on-chip oscillator has a high-gain, parallel-res-
onant amplifier for connection to a RC, crystal, ceramic res-
onator, LC, or any suitable external clock source (XTAL1
= Input, XTAL2 = Output). The crystal should be AT cut,
4 MHz max, with a series resistance (RS) less than or equal
to 100 ohms.
The crystal should be connected across XTAL1 and XTAL2
using the vendor’s crystal recommended capacitors from
each pin directly to device Ground pin 14 (Figure 14).
Note:
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To use a 32 kHz crystal, the 32 kHz operational mask option
must be selected, and an external resistor R must be con-
nected across XTAL1 and XTAL2. To use an RC oscillator,
the RC oscillator option must be selected.
HALT Mode.
This instruction turns off the internal CPU
clock (not the crystal oscillation). The counter/timers and
external interrupts IRQ0, IRQ1, IRQ2, and IRQ3 remain ac-
tive. The device can be recovered by interrupts, either ex-
ternally or internally generated. An interrupt request must
be executed (enabled) to exit HALT Mode. After the inter-
rupt service routine, the program continues from the in-
struction after the HALT.
STOP Mode.
This instruction turns off the internal clock
and external crystal oscillation, thereby reducing the stand-
by current. The STOP Mode can be released by two meth-
ods. The first method is a RESET of the device by removing
V
CC
or dropping the V
CC
below V
LV
. The second method
is if P27 is at a low level when the device executes the STOP
instruction. A Low condition on P27 releases the STOP
Mode regardless if configured for input or output.
Program execution under both conditions begins at location
000C (Hex). However, when P27 is used to release the
STOP Mode, the I/O port mode registers are not reconfig-
ured to their default power-on conditions. This condition
prevents any I/O, configured as output when the STOP in-
struction was executed, from glitching to an unknown state.
To use the P27 release approach with STOP Mode, use the
following instruction:
In order to enter STOP or HALT Mode, it is necessary to
first flush the instruction pipeline to avoid suspending ex-
ecution in mid-instruction. To execute this instruction, the
user must perform a NOP (opcode = FFH) immediately be-
fore the appropriate sleep instruction. The NOP is executed
as follows:
Watch-Dog Timer (WDT).
The Watch-Dog Timer is en-
abled by instruction WDT. When the WDT is enabled, it
cannot be stopped by the instruction. With the WDT in-
struction, the WDT should be refreshed once the WDT is
enabled within every Twdt period; otherwise, the Z8 resets
itself. The WDT instruction affects the Flags accordingly:
Z=1, S=0, V=0.
WDT = 5F (Hex)
LD
NOP
STOP
Note:
(X = dependent upon user’s application.)
P2M, #1XXX XXXXB
FF
6F
or
FF
7F
NOP
STOP
; clear the pipeline
; enter STOP Mode
NOP
HALT
; clear the pipeline
; enter HALT Mode
Figure 15. Oscillator Configuration
XTAL1
XTAL2
C1
C2
*
C1
*
C2
*
Ceramic
Resonator
or Crystal
External Clock
L
LC Clock
XTAL1
XTAL2
XTAL1
XTAL2
*
*
= Use pin 14.
XTAL1
XTAL2
C1
C2
Rf
Rd
32 KHz
32 KHz Crystal Clock
XTAL1
XTAL2
R
RC Clock
C
*
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