參數(shù)資料
型號(hào)： Z8612912SSC
廠商： ZILOG INC
元件分類： 消費(fèi)家電
英文描述： CAP 0.1UF 100V 10% X7R AXIAL TR-14
中文描述： SPECIALTY CONSUMER CIRCUIT, PDSO18
封裝： PLASTIC, SOIC-18
文件頁(yè)數(shù)： 5/50頁(yè)
文件大?。?/td> 927K
代理商： Z8612912SSC
Z86129/130/131
NTSC Line 21 Decoder
P R E L I M I N A R Y
DS96TEL0200
5
1
ELECTRICAL CHARACTERISTICS
Non Standard Video Signals must have the following characteristics:
Horizontal Signal Input (preferably H Flyback)
Line 21 Input Parameters (at 1.0V p-p)
Note:
Line 21 must be in its proper position to the leading edge of the Vertical Sync signal.
Timing Signals
Parameter
Sync Amplitude
Vertical Pulse Width
Vertical Pulse Tilt
H Timing
Conditions
200 mV minimum
3H
±
0.5H
20 mV maximum
Phase Step (Head Switch)
Fh Deviation (long term)
Fh p-p Deviation (short term)
The internal sync circuits will lock to all 525 or 625 line signals having a vertical
sync pulse that meets the following conditions:
1.
It is at least 2H wide.
2.
It starts at the proper 2H boundary for its field.
3.
If equalizing pulse serrations are present, they must be less than 0.125H in
width.
The Z86129/130/131 will function down to a 25 dB signal-to-noise ratio (CCIR
weighted) with one error per row or better at that level.
Input
±
10
μ
s maximum
±
0.5% maximum
±
0.3% maximum
Vertical Sync Signal
Minimum Signal-to-Noise
Ratio to Composite Video
Parameter
Amplitude
Video Lock Mode:
Conditions
CMOS level signal where Low <= 0.2 V
Polarity
Frequency
15,734.263 Hz
Polarity
Frequency
Same as Display Horizontal Flyback Pulse (HFB) pulse
CC
Any
±
3%
HIN Lock Mode:
Any
Parameter
Cod Amplitude
Code Zero Level
Start of Code
Conditions
50 IRE
5 IRE, +15 IRE relative to Back Porch
10.5
±
0.5
μ
s, (Measured from the midpoint of the falling edge of the last clock run-in cycle
to the midpoint of the rising edge of the start bit.)
3.972
μ
s, –0.00
μ
sec, +0.30
μ
s (Measured from the midpoint of the falling edge of the last
clock run-in cycle to the midpoint of the rising edge of the start bit.
Start of Data
Parameter
Dot
Dot Period
Character Cell Width
Width of Row (Box)
Width of Row (Char)
Horizontal Display Timing
Conditions
768 x FH = 12.0839 MHz
82.75 ns
1.324
μ
s (tH/48)
45.018
μ
s (34 chars = 17/24 x tH
42.370
μ
s (32 chars = 2/3 x tH
The timing of the output signals Box and RGB have been set to make a centered display.
The positioning of these outputs can be adjusted in 330 ns increments by writing a new
value to the Z86129 H Position Register (Address = 02h).
相關(guān)PDF資料
PDF描述
Z8613012PSC CAP 2200PF 100V 10% X7R AXIAL TR-14
Z8613012SSC CAP 2400PF 100V 10% X7R AXIAL TR-14
Z8613112PSC Ceramic Multilayer Capacitor; Capacitor Type:General Purpose; Capacitance:0.1uF; Capacitance Tolerance: 10%; Voltage Rating:100VDC; Capacitor Dielectric Material:Multilayer Ceramic; Termination:Axial Leaded RoHS Compliant: Yes
Z8613112SSC CAP 0.056UF 100V 10% X7R AXIAL TR-14
Z86160 SET-TOP CONTROLLER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
Z8612912SSC00TR 功能描述:IC CLOSED CAPTION DECODER 18SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799
Z8612912SSG 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 CC DECODER RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray
Z8612912SSG00TR 制造商:Zilog Inc 功能描述:Z86129 Series 5 V Surface Mount NTSC Line 21 Decoder - SOIC-18
Z8613 制造商:ZILOG 制造商全稱:ZILOG 功能描述:Full-duplex UART and two programmable 8-bit counter/timers, each with a 6-bit
Z86130 制造商:ZILOG 制造商全稱:ZILOG 功能描述:NTSC LINE 21 DECIDER
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*