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參數(shù)資料
| 型號： | Z8613012SSC |
| 廠商： | ZILOG INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | CAP 2400PF 100V 10% X7R AXIAL TR-14 |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO18 |
| 封裝： | PLASTIC, SOIC-18 |
| 文件頁數(shù)： | 30/50頁 |
| 文件大小： | 927K |
| 代理商： | Z8613012SSC |
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Z86129/130/131
NTSC Line 21 Decoder
P R E L I M I N A R Y
30
DS96TEL0200
INTERNAL REGISTERS
(Continued)
D
5
-D
7
-s
0
-s
2
.
Selects a set of secondary parameters,
tabulated below, to be used in filtering the XDS data when
XDS recovery has been enabled.
Interrupt Request Register Address = 06h
D
0
-res.
Reserved.
D
1
-DLE.
Active High, indicating that the data line has
ended. This bit will clear in each field a few lines after row
15.
D
2
-EOF.
Active High, indicating that the video signal is
currently at the end of a field. This bit will clear in each field
a few lines after row 15.
D
3
-dLOK.
Active High, indicating that the state of the
LOCK signal has changed. The SS register must be read
to determine the current state.
D
4
-dSCH.
Active High, indicating that a change in selected
channel activity has occurred. The Line 21 Activity register
must be read in order to determine if the selected data
channel is active.
D
5
-dXDS.
Active High, indicating that a change in XDS
activity has occurred. The Line 21 Activity register must be
read to determine if XDS data is active.
D
6
-dCAP.
Active High, indicating that a change in a
caption data channel activity has occurred. The Caption
Activity Register (Address 08h) must be read to determine
exactly which caption channels are now active.
D
7
-dTXT.
Active High, indicating that a change in a TEXT
data channel activity has occurred. The Caption Activity
Register (Address 08h) must be read to determine exactly
which TEXT channels are now active.
Note:
Except as noted for the case of D1 and D2 above,
the master device must write a 1 to the appropriate bit in
the Interrupt Request Register to clear the Interrupt.
Writing a 1 to any valid bit position the Interrupt Request
Register is equivalent to CLEARing a interrupt request on
that bit.
Interrupt Mask Register Address = 07h
This register identifies which activities in the Interrupt
Request Register will be used to cause an interrupt.
Setting a bit to a 1 enables the interrupt when the
corresponding event becomes active. Setting all bits of this
register to zero disables interrupts.
Table 13. XDS Secondary Filter Settings
Secondary Filter
All
Time Information
In Band Only
Program Rating (Note #4)
VCR Information
Reserved
Reserved
Reserved
Filter Value (s0:s2)
0h
1h
2h
3h
4h
5h
6h
7h
Notes:
1. Setting this register to 00h turns XDS data recovery off.
Setting bits D
0
through D
4
enables XDS data recovery for
the Classes selected as qualified by the Secondary Filter
(bits D
5
-D
7
). If Bits D
0
-D
4
are all set to 1, all Classes of XDS
data will be output (even Reserved and Undefined).
2. The Time Information Only selection includes the Time of
Day (TOD) and Local Time Zone (LTZ) packets.
3. VCR Information will select TOD, LTZ, Net ID, Local Call
Letters, Impulse Capture, Tape Delay, Composite 2 and
Out of Band Channel Number packets for recovery.
4. Program rating filter available on Z86129 and Z86130
only.
Figure 25. Interrupt Request Register (Address = 06h)
Bit
R
R
R
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
R/W
R/W
R/W
R/W
R/W
dLOK
EOF
DLE
res
dTXT
dCAP
dXDS
dSCH
Figure 26. Interrupt Mask Register Address = 07h
Bit
R/W
R/W
R/W
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
R/W
R/W
R/W
R/W
R/W
dLOK
EOF
DLE
DAV
dTXT
dCAP
dXDS
dSCH
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