參數(shù)資料
型號： Z86131
廠商： ZiLOG, Inc.
英文描述： NTSC LINE 21 DECIDER
中文描述： NTSC制式線21決勝局
文件頁數(shù)： 21/50頁
文件大?。?/td> 927K
代理商： Z86131
Z86129/130/131
NTSC Line 21 Decoder
P R E L I M I N A R Y
DS96TEL0200
21
1
The master's sequence for reading two
data bytes
(total
of three bytes including SSB) from the Z86129/130/131 is
given as:
Start-Slave Address Read/Slave ACK-SS Byte/Master
ACK-Byte (slave)/Master ACK-Byte (slave)/Master NACK-
Stop
Clock and Data Transitions.
The SCK and SDA bus lines
are normally pulled High with a resistor. Data on the SDA
bus may only change during SCK Low time periods. Data
changes during SCK High periods will indicate a start or
stop condition as defined in Table 7.
Start Condition.
A High-to-Low transition of SDA with
SCK High is a start condition which must precede any
other command.
Stop Condition.
A Low-to-High transition of SDA with
SCK High is a stop condition which terminates all
communications.
Acknowledge.
All address and data words are serially
transmitted to and from the Z86129/130/131 in eight bit
words. A ninth bit time is used for the acknowledge. The
acknowledging device does so by pulling the SDA bus Low
during the ninth bit. A Not Acknowledge (NACK) is given
by SDA=High during the ninth clock time.
Figure 10. I
2
C Bus READ (Command)
STRT
STOP
SLAVE
ADDR
SERIAL
STATUS
(READ=29h)
(SSB)
NACK
STRT
STOP
SLAVE
ADDR
SERIAL
STATUS
(READ=29h)
(SSB)
READ
DATA1
NACK
STRT
STOP
SLAVE
ADDR
SERIAL
STATUS
(READ=29h)
(SSB)
READ
DATA1
READ
DATA2
NACK
I2C-One Byte Write (Status Only)
I2C-Two Byte Read (Status & Data1)
I2C-Three Byte Read (Status, Data1, & Data2)
Note:
In all I
2
C Read operations defined herein, the last byte read
from the Z86129/130/131 must be acknowledged by the master
with a NACK (Not ACKnowledge).
Figure 11. I
2
C Serial Timing
SDA (IN)
SCK
t
SU.STA
SDA (OUT)
t
HD.STA
t
AA
t
F
t
High
t
Low
t
HD.DAT
t
SU.DAT
t
DH
t
R
t
SU.STO
t
BUF
Table 7. I
2
C Serial Timing Min/max
Symbol
f
SCK
t
LOW
t
High
t
R
t
F
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
SU.STO
t
DH
t
I
Parameter
Clock Frequency
Clock Pulse Width Low
Clock Pulse Width High
SDA and SCL Rise Time
SDA and SCL Fall Time
Clock Low to Data Out Valid
Bus Free Time
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Stop Set-up Time
Data Out Hold Time
Input Filter Time Constant
Min
Max
100
–
–
1.0
300
3.5
–
–
–
–
–
–
–
100
Units
kHz
μ
s
μ
s
μ
s
ns
μ
s
μ
s
μ
s
μ
s
μ
s
ns
μ
s
ns
ns
4.7
4.0
–
–
0.1
4.7
4.0
4.7
0
250
4.7
100
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PDF描述
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