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Z86307
8-Bit CMOS Z8 MCU For PS/2 Mouse and Trackball Applications
ZiLOG
17
P R E L I M I N A R Y
DS007400-PER0399
Interrupts.
The Z86307 features four interrupts from four
different sources. These interrupts are maskable and prior-
itized (Figure 19). The four sources are divided as follows:
the falling edge of P31, P33, and the two counter/timers.
The Interrupt Mask Register globally or individually en-
ables or disables the four interrupt requests (Table 4).
When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder that is con-
trolled by the Interrupt Priority register. All Z86307 inter-
rupts are vectored through locations in program memory.
When an interrupt machine cycle is activated, an interrupt
request is granted. This disables all subsequent interrupts,
saves the Program Counter and Status Flags, and then
branches to the program memory vector location reserved
for that interrupt. This memory location and the next byte
contain the 16-bit starting address of the Interrupt Service
Routine for that particular interrupt request.
To accommodate polled interrupt systems, interrupt inputs
are masked and the Interrupt Request Register is polled to
determine which of the interrupt requests needs service.
Table 4. Interrupt Types, Sources, and Vectors
Source
P33
P31
T0
T1
Name
IRQ1
IRQ2
IRQ4
IRQ5
Vector
2,3
4,5
8,9
10,11
Location
External
External
Internal
Internal
Comments
Falling Edge
Falling Edge
Note:
IRQ0 and IRQ2 are disabled.
Figure 19. Interrupt Block Diagram
IRQ
IMR
IPR
Priority
Logic
6
Vector Select
Global
Interrupt
Enable
Interrupt
Request
IRQ0–IRQ5