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參數(shù)資料
| 型號： | Z8631904SSC |
| 廠商： | ZILOG INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PS/2 MOUSE CONTROLLER |
| 中文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO18 |
| 封裝： | SOIC-18 |
| 文件頁數(shù)： | 16/23頁 |
| 文件大小： | 278K |
| 代理商： | Z8631904SSC |
Z86319
PS/2 Mouse Controller
Zilog
16
P R E L I M I N A R Y
DS97KEY1605
FUNCTIONAL DESCRIPTION
(Continued)
Interrupts.
The Z86319 features four interrupts from
four different sources. These interrupts are maskable and
prioritized (Figure 17). The four sources are divided as fol-
lows: the falling edge of P31, P33, and the two
counter/timers. The Interrupt Mask Register globally or in-
dividually enables or disables the four interrupt requests
(Table 5).
When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder that is con-
trolled by the Interrupt Priority register. All Z86319 inter-
rupts are vectored through locations in program memory.
When an interrupt machine cycle is activated, an interrupt
request is granted, thereby disabling all subsequent inter-
rupts, saving the Program Counter and Status Flags, and
branching to the program memory vector location reserved
for that interrupt. This memory location and the next byte
contain the 16-bit starting address of the Interrupt Service
Routine for that particular interrupt request.
To accommodate polled interrupt systems, interrupt inputs
are masked and the Interrupt Request Register is polled to
determine which of the interrupt requests requires service.
Table 5. Interrupt Types, Sources, and Vectors
Source
P33
P31
T0
T1
Name
IRQ1
IRQ2
IRQ4
IRQ5
Vector
2,3
4,5
8,9
10,11
Location Comments
External
Falling Edge
External
Falling Edge
Internal
Internal
Figure 17. Interrupt Block Diagram
IRQ
IMR
IPR
Priority
Logic
6
Vector Select
Global
Interrupt
Enable
Interrupt
Request
IRQ1 - IRQ5
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| Z863-21 | 制造商:Neutrik USA Inc 功能描述:CAP RED |
| Z863-22 | 制造商:Neutrik USA Inc 功能描述:CAP GREEN |
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| Z863-24 | 制造商:Neutrik USA Inc 功能描述:CAP BLUE |
| Z863-25 | 制造商:Neutrik USA Inc 功能描述:CAP BLACK |
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