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參數(shù)資料
| 型號： | Z86418 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | Z8 8-BIT Mouse Controller(8位CMOS鼠標微控制器) |
| 中文描述： | Z8 8位鼠標控制器（8位的CMOS鼠標微控制器） |
| 文件頁數(shù)： | 19/27頁 |
| 文件大小： | 340K |
| 代理商： | Z86418 |
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Z86418
Zilog
Z8 8-Bit Mouse Controller
DS97KEY1404
P R E L I M I N A R Y
19
1
Interrupts
. The Z86418 features six interrupts from six dif-
ferent sources. These interrupts are maskable and priori-
tized (Figure 16). The six sources are divided as follows:
the falling edge on P31, P32, P33, the rising edge on P33
and the two counter/timers. The Interrupt Mask Register
globally or individually enables or disables the four inter-
rupt requests (Table 3).
When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder that is con-
trolled by the Interrupt Priority register. All Z86418 inter-
rupts are vectored through locations in program memory.
When an interrupt machine cycle is activated, an interrupt
request is granted, thereby disabling all subsequent inter-
rupts, saving the Program Counter and Status Flags, and
branching to the program memory vector location reserved
for that interrupt. This memory location and the next byte
contain the 16-bit starting address of the Interrupt Service
Routine for that particular interrupt request.
To accommodate polled interrupt systems, interrupt inputs
are masked and the Interrupt Request Register is polled to
determine which of the interrupt requests requires service.
Table 3. Interrupt Types, Sources, and Vectors
Source Name
P33
P33
P32
P31
T0
T1
Vector Location Comments
2,3
External (F)Edge Triggered
6,7
External (R)Edge Triggered
0,1
External (F)Edge Triggered
4,5
External (F)Edge Triggered
8,9
Internal
10,11
Internal
IRQ1
IRQ3
IRQ0
IRQ2
IRQ4
IRQ5
Figure 16. Interrupt Block Diagram
IRQ
IMR
IPR
Priority
Logic
6
Vector Select
Global
Interrupt
Enable
Interrupt
Request
IRQ0 - IRQ5
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