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參數(shù)資料
| 型號： | Z86C0208SSC |
| 廠商： | ZILOG INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | LOW-COST, 512-BYTE ROM MICROCONTROLLERS |
| 中文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO18 |
| 封裝： | SOIC-18 |
| 文件頁數(shù)： | 22/36頁 |
| 文件大?。?/td> | 898K |
| 代理商： | Z86C0208SSC |
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Z86C02/E02/L02
Low-Cost, 512-Byte ROM Microcontrollers
1-22
P R E L I M I N A R Y
DS96DZ80301 (11/96)
FUNCTIONAL DESCRIPTION
(Continued)
Interrupts.
The Z8 has five interrupts from four different
sources. These interrupts are maskable and prioritized
(Figure 16). The sources are divided as follows: the falling
edge of P31 (AN1), P32 (AN2), P33 (REF), the rising edge
of P32 (AN2), and one counter/timer. The Interrupt Mask
Register globally or individually enables or disables the
five interrupt requests (Table 5).
When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder that is con-
trolled by the Interrupt Priority register. All Z8 interrupts are
vectored through locations in program memory. When an
Interrupt machine cycle is activated, an Interrupt Request
is granted. This disables all subsequent interrupts, saves
the Program Counter and Status Flags, and then branches
to the program memory vector location reserved for that in-
terrupt. This memory location and the next byte contain the
16-bit starting address of the interrupt service routine for
that particular interrupt request.
To accommodate polled interrupt systems, interrupt inputs
are masked and the interrupt request register is polled to
determine which of the interrupt requests needs service.
User must select any Z86E08 mode in Zilog's C12 ICE-
BOX emulator. The rising edge interrupt is not directly
supported on the Z86CCP00ZEM emulator.
Figure 15. Counter/Timers Block Diagram
OSC
÷
2
6-Bit
Down
Counter
8-Bit
Down
Counter
PRE1
Initial Value
Register
T1
Initial Value
Register
T1
Current Value
Register
Clock
Logic
IRQ5
Internal Data Bus
Write
Write
Read
Internal Clock
Gated Clock
Triggered Clock
T P31
External Clock
Internal
Clock
÷
4
*
Table 5. Interrupt Types, Sources, and Vectors
Vector
Location
0,1
2,3
4,5
6,7
8,9
10,11
Name
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
Notes:
F = Falling edge triggered
R = Rising edge triggered
Source
AN2(P32)
REF(P33)
AN1(P31)
AN2(P32)
Reserved
T1
Comments
External (F)Edge
External (F)Edge
External (F)Edge
External (R)Edge
Reserved
Internal
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