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CP96DZ82900
15
Z86C30/C31/C32/C40
CP96DZ82900
Z
ILOG
AC ELECTRICAL CHARACTERISTICS
Additional Timing Table (Divide-By-One Mode)
T
A
= 0
°
C to +70
°
C
T
A
= 40
°
C to +105
°
C
V
4 MHz
Min
4 MHz
Min
No Symbol
Parameter
Note [6]
Max
Max
Units
Notes
1
TpC
Input Clock Period
3.0V
5.5V
3.0V
5.5V
250
250
DC
DC
25
25
250
250
DC
DC
25
25
ns
ns
ns
ns
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
2
TrC,TfC
Clock Input Rise & Fall Times
3
TwC
Input Clock Width
3.0V
5.5V
3.0V
5.5V
100
100
100
70
100
100
100
70
ns
ns
ns
ns
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
4
TwTinL
Timer Input LowWidth
5
TwTinH
Timer Input High Width
3.0V
5.5V
3.0V
5.5V
5TpC
5TpC
8TpC
8TpC
5TpC
5TpC
8TpC
8TpC
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
6
TpTin
Timer Input Period
7
TrTin,
TfTin
TwIL
Timer Input Rise & Fall Timer
3.0V
5.5V
3.0V
5.5V
100
100
100
100
ns
ns
ns
ns
[1,7,8]
[1,7,8]
[1,2,7,8]
[1,2,7,8]
8A
Int. Request LowTime
100
70
100
70
8B
TwIL
Int. Request LowTime
3.0V
5.5V
3.0V
5.5V
5TpC
5TpC
5TpC
5TpC
5TpC
5TpC
5TpC
5TpC
[1,3,7,8]
[1,3,7,8]
[1,2,7,8]
[1,2,7,8]
9
TwIH
Int. Request Input High Time
10
Twsm
STOP Mode Recovery Width Spec 3.0V
12
12
12
12
ns
ns
[4,8]
[4,8]
[4,8,9]
[4,8,9]
5.5V
3.0V
5.5V
11
Tost
Oscillator Start-up Time
5TpC
5TpC
5TpC
5TpC
Notes:
[1] Timing Reference uses 0.7 V
for a logic 1 and 0.2 V
CC
for a logic 0.
[2] Interrupt request via Port 3 (P31-P33).
[3] Interrupt request via Port 3 (P30).
[4] SMR-D5 = 1, POR STOP Mode Delay is on.
[5] Reg. WDTMR.
[6] The V
CC
voltage specification of 3.0V guarantees 3.3V
±
0.3V, and
the V
voltage specification of 5.5V guarantees 5.0V
±
0.5V.
[7] SMR D1 = 0.
[8] Maximum frequency for internal system clock is 4 MHz when
using XTAL divide-by-one mode.
[9] For RC and LC oscillator, and for oscillator driven by clock driver.