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| 型號(hào)： | Z86C6116PSC |
| 廠商： | ZILOG INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | TRANS NPN 400VCEO 7A TO-220F |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 22/46頁 |
| 文件大?。?/td> | 388K |
| 代理商： | Z86C6116PSC |
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22
Z86C61/62/96
Z8
M
ICROCONTROLLER
FUNCTIONAL DESCRIPTION
(Continued)
Expanded Register File.
The register file has been ex-
panded to allow for additional system control registers,
and for mapping of additional peripheral devices along
with I/O ports into the register address area. The Z8
register address space R0 through R15 has now been
implemented as 16 groups of 16 registers per group.
These register groups are known as the ERF (Expanded
Register File). Bits 7-4 of Register RP select the working
register group. Bits 3-0 of Register RP select the expanded
register group (Figure 21). Eight I/O port registers reside in
the Expanded Register File at Bank F. The rest of the
Expanded Register is not physically implemented and is
open for future expansion.
The upper nibble of the register pointer (Figure 20) selects
which group of 16 bytes in the register file, out of the full
256, will be accessed. The lower nibble selects the ex-
panded register file bank and in the case of the Z86C61/
62/96, only Bank F is implemented. A 0H in the lower nibble
will allow the normal register file to be addressed, but any
other value from 1H to FH will exchange the lower 16
registers in favor of an expanded register group of 16
registers.
For example:
Z86C61: (See Figures 18 and 19)
R253 RP = 00H
R0 = Port 0
R1 = Port 1
R2 = Port 2
R3 = Port 3
But If:
R253 RP = 0FH
R0 = Reserved
R1 = Reserved
R2 = Port 4
R3 = Port 4, Direction Register
R9 = Port 6, Mode Register
Further examples:
SRP #0FH
LD R2, #10010110
Set working group 0 and Bank F
Load value into Port 4 using
working register addressing.
Load value into Port 4 using
absolute addressing.
Load value into Port 6 mode.
Set working group 1 and Bank F
Load value into general purpose
register 12H
Load value into general purpose
register 12H
Load value into Port 4
LD 2, #10010110
LD 9, #11110000
SRP #1FH
LD R2, #11010110
LD 12H, #11010110
LD 2, #10010110
RAM Protect.
The upper portion of the RAM’s address
spaces 80FH to EFH (excluding the control registers) can
be protected from reading and writing. The RAM Protect
bit option is mask-programmable and is selected by the
customer when the ROM code is submitted. After the mask
option is selected, the user can activate from the internal
ROM code to turn off/on the RAM Protect by loading a bit
D6 in the IMR register to either a 0 or a 1, respectively. A
1 in D6 indicates RAM Protect enabled.
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