參數(shù)資料
型號： Z86C8416VSC
廠商： ZILOG INC
元件分類： 微控制器/微處理器
英文描述： Z8 MCU MICROCONTROLLERS
中文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC28
封裝： PLASTIC, LCC-28
文件頁數(shù)： 40/46頁
文件大小： 957K
代理商： Z86C8416VSC
Z86C83/C84
Z8
MCU Microcontrollers
40
DS96DZ80203
EXPANDED REGISTER FILE CONTROL REGISTERS
Figure 47. Stop-Mode Recovery Register
(Write-Only, except Bit 7 which is Read-Only)
Figure 48. Watch-Dog Timer Mode Register 2
D7
D6 D5
D4
D3
D2
D1
D0
(
)
SCLK/TCLK Divide-by-16
0 OFF* *
1 ON
Stop-Mode Recovery Source
000 POR Only and/or External Reset*
001 Reserved
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON
Stop Recovery Level
0 Low *
1 High
Stop Flag (Read-Only)
0 POR
1 Stop Recovery
Note: Not used in conjunction with SMR2
Source
* Default Setting After RESET
** Default setting after RESET and
Stop-Mode Recovery
*
*
External Clock Divide-by-2
0 SCLK/TCLK = XTAL/2*
1 SCLK/TCLK = XTAL
D7
D6
D5
D4
D3
D2
D1
D0
SMR2 (0F) DH
Note: Not used in conjunction with SMR Source
Stop-Mode Recovery Source 2
00 POR only*
01 AND P20,P21,P22,P23
10 AND P20,P21,P22,P23,
P24,P25,P26,P27
Reserved (Must be 0)
Figure 49. Watch-Dog Timer Mode Register
(Write-Only)
Figure 50. Port Configuration Register (PCON)
(Write-Only)
D7
D6
D5
D4
D3
D2
D1
D0
WDTMR (F) 0F
WDT TAP
00 256 SCLK
01 512 SCLK *
10 1024 SCLK
11 4096 SCLK
WDT During HALT
0 OFF
1 ON
*
WDT During STOP
0 OFF
1 ON
*
XTAL1/INT RC Select for WDT
0 On-Board RC
1 XTAL
Reserved (Must be 0)
*
Default setting after RESET
XTAL=SCLK/TCLK shown
*
D7
D6
D5
D4
D3
D2
D1
D0
Comparator
Output Port 3
0 P34 Standard Output
*
1 P34 Comparator Output
Reserved (Must be 1.)
PCON (F) 00
* Default setting from Stop-Mode Recovery,
Power-On Reset, and any WDT Reset.
0 Port 0 Open-Drain
1 Port 0 Push-Pull*
Reserved (Must be 1.)
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