參數(shù)資料
型號(hào)： Z86E0412PSC1924
廠商： ZILOG INC
元件分類： 微控制器/微處理器
英文描述： CMOS Z8 OTP Microcontrollers
中文描述： 8-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PDIP18
封裝： PLASTIC, DIP-18
文件頁(yè)數(shù)： 19/44頁(yè)
文件大小： 251K
代理商： Z86E0412PSC1924
Z86E04/E08
Zilog
CMOS Z8 OTP Microcontrollers
DS97Z8X0401
P R E L I M I N A R Y
19
1
LOW NOISE VERSION
Low EMI Emission
The Z86E04/E08 can be programmed to operate in a Low
EMI Emission Mode by means of a mask ROM bit option.
Use of this feature results in:
I
All pre-driver slew rates reduced to 10 ns typical.
I
Internal SCLK/TCLK operation limited to a maximum of
4 MHz - 250 ns cycle time.
I
Output drivers have resistances of 500 Ohms (typical).
I
Oscillator divide-by-two circuitry eliminated.
The Low EMI Mode is mask-programmable to be selected
by the customer at the time the ROM code is submitted.
PIN FUNCTIONS
OTP Programming Mode
D7-D0
Data Bus. Data can be read from, or written to, the
EPROM through this data bus.
V
CC
Power Supply.It is typically 5V during EPROM Read
Mode and 6.4V during the other modes (Program, Pro-
gram Verify, and so on).
/CE
Chip Enable(active Low). This pin is active during
EPROM Read Mode, Program Mode, and Program Verify
Mode.
/OE
Output Enable(active Low). This pin drives the Data
Bus direction. When this pin is Low, the Data Bus is output.
When High, the Data Bus is input.
EPM
EPROM Program Mode.This pin controls the differ-
ent EPROM Program Modes by applying different
voltages.
V
PP
Program Voltage.This pin supplies the program volt-
age.
Clear
Clear(active High). This pin resets the internal ad-
dress counter at the High Level.
Clock
Address Clock. This pin is a clock input. The internal
address counter increases by one with one clock cycle.
/PGM
Program Mode(active Low). A Low level at this pin
programs the data to the EPROM through the Data Bus.
Application Precaution
The production test-mode environment may be enabled
accidentally during normal operation if
excessive noise
surges above V
cc
occur on the XTAL1 pin.
In addition, processor operation of Z8 OTP devices may be
affected by
excessive noise
surges on the V
pp
, /CE,
/EPM, /OE pins while the microcontroller is in Standard
Mode.
Recommendations for dampening voltage surges in both
test and OTP Mode include the following:
I
Using a clamping diode to V
CC
.
I
Adding a capacitor to the affected pin.
Note:
Programming the EPROM/Test Mode Disable
option will prevent accidental entry into EPROM Mode or
Test Mode.
相關(guān)PDF資料
PDF描述
Z86E0412SEC CMOS Z8 OTP Microcontrollers
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相關(guān)代理商/技術(shù)參數(shù)
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