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參數(shù)資料
| 型號： | Z86E04 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | CMOS Z8 OTP Microcontroller(CMOS 8位一次可編程微控制器) |
| 中文描述： | 檢察官辦公室的CMOS Z8微控制器（的CMOS 8位一次可編程微控制器） |
| 文件頁數(shù)： | 23/44頁 |
| 文件大?。?/td> | 211K |
| 代理商： | Z86E04 |
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Z86E04/E08
Zilog
CMOS Z8 OTP Microcontrollers
DS97Z8X1104
P R E L I M I N A R Y
23
1
Comparator Inputs.
Two analog comparators are added
to input of Port 3, P31, and P32, for interface flexibility. The
comparators reference voltage P33 (REF) is common to
both comparators.
Typical applications for the on-board comparators; Zero
crossing detection, A/D conversion, voltage scaling, and
threshold detection. In Analog Mode, P33 input functions
serve as a reference voltage to the comparators.
The dual comparator (common inverting terminal) features
a single power supply which discontinues power in STOP
Mode. The common voltage range is 0–4 V when the V
CC
is 5.0V; the power supply and common mode rejection ra-
tios are 90 dB and 60 dB, respectively.
Interrupts are generated on either edge of Comparator 2's
output, or on the falling edge of Comparator 1's output.
The comparator output is used for interrupt generation,
Port 3 data inputs, or T
IN
through P31. Alternatively, the
comparators can be disabled, freeing the reference input
(P33) for use as IRQ1 and/or P33 input.
FUNCTIONAL DESCRIPTION
The following special functions have been incorporated
into the Z8 devices to enhance the standard Z8 core archi-
tecture to provide the user with increased design flexibility.
RESET
. This function is accomplished by means of a Pow-
er-On Reset or a Watch-Dog Timer Reset. Upon power-
up, the Power-On Reset circuit waits for T
POR
ms, plus 18
clock cycles, then starts program execution at address
000C (Hex) (Figure 10). The Z8 control registers' reset val-
ue is shown in Table 3.
Power-On Reset (POR).
A timer circuit clocked by a ded-
icated on-board RC oscillator is used for a POR timer func-
tion. The POR time allows V
CC
and the oscillator circuit to
stabilize before instruction execution begins. The POR
timer circuit is a one-shot timer triggered by one of the four
following conditions:
I
Power-bad to power-good status
I
Stop-Mode Recovery
I
WDT time-out
I
WDH time-out
Watch-Dog Timer Reset.
The WDT is a retriggerable
one-shot timer that resets the Z8 if it reaches its terminal
count. The WDT is initially enabled by executing the WDT
instruction and is retriggered on subsequent execution of
the WDT instruction. The timer circuit is driven by an on-
board RC oscillator.
Figure 10. Internal Reset Configuration
INT OSC
XTAL OSC
POR
(Cold Start)
P27
(Stop Mode)
18 CLK
Reset Filiter
Chip Reset
Delay Line
TPOR msec
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