參數(shù)資料
型號: Z86E3016ESE
廠商: ZILOG INC
元件分類: 微控制器/微處理器
英文描述: Z8 4K OTP Microcontroller
中文描述: 8-BIT, UVPROM, 16 MHz, MICROCONTROLLER, CDIP28
封裝: WINDOWED, HERMETIC SEALED, CERDIP-28
文件頁數(shù): 45/66頁
文件大?。?/td> 453K
代理商: Z86E3016ESE
Z86E30/E31/E40
Zilog
Z8 4K OTP Microcontroller
DS97Z8X0500
P R E L I M I N A R Y
45
1
SCLK/TCLK Divide-by-16 Select
(D0). This bit of the
SMR controls a divide-by-16 prescaler of SCLK/TCLK.
The purpose of this control is to selectively reduce device
power consumption during normal processor execution
(SCLK control) and/or HALT mode (where TCLK sources
counter/timers and interrupt logic).
External Clock Divide-by-Two
(D1). This bit can elimi-
nate the oscillator divide-by-two circuitry. When this bit is
0, the System Clock (SCLK) and Timer Clock (TCLK) are
equal to the external clock frequency divided by two. The
SCLK/TCLK is equal to the external clock frequency when
this bit is set (D1=1). Using this bit together with D7 of
PCON further helps lower EMI (i.e., D7 (PCON) = 0, D1
(SMR) = 1). The default setting is zero.
STOP-Mode Recovery Source
(D2, D3, and D4). These
three bits of the SMR register specify the wake up source
of the STOP-Mode Recovery (Figure 32). Table 12 shows
the SMR source selected with the setting of D2 to D4. P33-
P31 cannot be used to wake up from STOP mode when
programmed as analog inputs. When the STOP-Mode Re-
covery sources are selected in this register then SMR2
register bits D0, D1 must be set to zero.
Note:
If the Port2 pin is configured as an output, this output
level will be read by the SMR circuitry..
Figure 32. STOP-Mode Recovery Source
P30
P31
P32
P33
P27
Stop-Mode Recovery Edge
Select (SMR)
P33 From Pads
Digital/Analog Mode
Select (P3M)
To P33 Data
Latch and IRQ1
To POR
RESET
SMR
SMR
SMR
D4 D3 D2
0 0 1
0 1 0
0 1 1
D4 D3 D2
1 0 0
D4 D3 D2
1 0 1
MUX
SMR
SMR
D4 D3 D2
1 1 0
D4 D3 D2
1 1 1
P20
P23
P20
P27
SMR2
SMR2
D1 D0
0 1
D1 D0
1 0
P20
P23
P20
P27
SMR
D4 D3 D2
0 0 0
VDD
SMR2 D1 D0
0 0
VDD
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