![](http://datasheet.mmic.net.cn/290000/Z86E4016VSE_datasheet_16189752/Z86E4016VSE_23.png)
Z86E30/E31/E40
Zilog
Z8 4K OTP Microcontroller
DS97Z8X0500
P R E L I M I N A R Y
23
1
Additional Timing Table
T
A
= -40
°
C to +105
°
C
16 MHz
No
Symbol
TpC
Parameter
Input Clock Period
V
CC
Note [6]
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
Min
62.5
62.5
Max
DC
DC
15
15
Units
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
Notes
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
1,7,8
[1,7,8
1,7,8
1,7,8
1,7,8
1,2,7,8
1,2,7,8
1,3,7,8
1,3,7,8
1,2,7,8
1
2
TrC,TfC
Clock Input Rise &
Fall Times
Input Clock Width
3
TwC
31
31
70
70
5TpC
5TpC
8TpC
8TpC
4
TwTinL
Timer Input Low
Width
Timer Input High
Width
Timer Input Period
5
TwTinH
6
TpTin
7
TrTin, TfTin Timer Input Rise
& Fall Timer
TwIL
Int. Request Low
Time
TwIL
Int. Request Low
Time
TwIH
Int. Request Input
High Time
Twsm
STOP Mode
Recovery Width
Spec
Tost
Oscillator Startup
Time
Twdt
Watch-Dog Timer
Delay Time
Before Timeout
100
100
ns
ns
ns
ns
8A
70
70
8B
5TpC
5TpC
5TpC
9
10
12
12
ns
ns
4,8
4,8
11
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
5TpC
5TpC
4,8
4,8
5,11
5,11
5,11
5,11
5,11
5,11
5,11
5,11
12
10
5
20
10
40
20
160
80
ms
ms
ms
ms
ms
ms
ms
ms
D0 = 0
D1 = 0
D0 = 1
D1 = 0
D0 = 0
D1 = 1
D0 = 1
D1 = 1
Notes:
1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0
2. Interrupt request via Port 3 (P31-P33)
3. Interrupt request via Port 3 (P30)
4. SMR-D5 = 1, POR STOP Mode Delay is on
5. Reg. WDTMR
6. The VCC voltage spec. of 5.5V guarantees 5.0V +/-
±
0.5V
7. SMR D1 = 0
8. Maximum frequency for internal system clock is 4 MHz when using
XTAL divide-by-one mode.
9. For RC and LC oscillator, and for oscillator driven by clock driver.
10. Standard Mode (not Low EMI output ports)
11. Using internal RC