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參數(shù)資料
| 型號： | Z86E31 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | Z8 2K OTP Microcontroller( Z8系列2k ROM一次可編程微控制器) |
| 中文描述： | Z8 2K檢察官辦公室的微控制器（Z8系列2k光盤一次可編程微控制器） |
| 文件頁數(shù)： | 40/64頁 |
| 文件大?。?/td> | 391K |
| 代理商： | Z86E31 |
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Z86E30/E31/E40
Z8 4K OTP Microcontroller
Zilog
40
P R E L I M I N A R Y
DS97Z8X0502
FUNCTIONAL DESCRIPTION
(Continued)
Power-On Reset (POR).
A timer circuit clocked by a ded-
icated on-board RC oscillator is used for the Power-On Re-
set (POR) timer function. The POR timer allows V
CC
and
the oscillator circuit to stabilize before instruction execu-
tion begins.
The POR timer circuit is a one-shot timer triggered by one
of three conditions:
1.
Power fail to Power OK status
2.
Stop-Mode Recovery (if D5 of SMR=0)
3.
WDT time-out
The POR time is a nominal 5 ms. Bit 5 of the STOP mode
Register (SMR) determines whether the POR timer is by-
passed after STOP-Mode Recovery (typical for an external
clock and RC/LC oscillators with fast start up times).
HALT.
Turns off the internal CPU clock, but not the XTAL
oscillation. The counter/timers and external interrupt IRQ0,
IRQ1, and IRQ2 remain active. The device is recovered by
interrupts, either externally or internally generated. An in-
terrupt request must be executed (enabled) to exit HALT
Mode. After the interrupt service routine, the program con-
tinues from the instruction after the HALT.
In order to enter STOP or HALT Mode, it is necessary to
first flush the instruction pipeline to avoid suspending exe-
cution in mid-instruction. To do this, the user must execute
a NOP (Opcode=FFH) immediately before the appropriate
sleep instruction, that is:
STOP.
This instruction turns off the internal clock and ex-
ternal crystal oscillation and reduces the standby current
to 10 microamperes or less. STOP Mode is terminated by
one of the following resets: either by WDT time-out, POR,
a Stop-Mode Recovery Source, which is defined by the
SMR register or external reset. This causes the processor
to restart the application program at address 000CH.
Port Configuration Register (PCON).
The PCON regis-
ter configures the ports individually; comparator output on
Port 3, open-drain on Port 0 and Port 1, low EMI on Ports
0, 1, 2 and 3, and low EMI oscillator. The PCON register is
located in the expanded register file at Bank F, location 00
(Figure 30).
FF
6F
NOP
STOP
or
NOP
HALT
; clear the pipeline
; enter STOP Mode
; clear the pipeline
; enter HALT Mode
FF
7F
Figure 30. Port Configuration Register (PCON)
(Write Only)
0 Port 0 Open Drain
1 Port 0 Push-pull Active*
D7
D6
D5
D4
D3
D2
D1
D0
PCON (FH) 00H
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
0 Port 0 Low EMI
1 Port 0 Standard*
0 Port 2 Low EMI
1 Port 2 Standard*
Low EMI Oscillator
0 Low EMI
1 Standard*
0 Port 3 Low EMI
1 Port 3 Standard*
* Default Setting After Reset
0 Port 1 Open Drain
1 Port 1 Push-pull Active*
0 Port 1 Low EMI
1 Port 1 Standard*
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