參數(shù)資料
型號(hào): Z86E34
廠商: ZiLOG, Inc.
英文描述: CMOS Z8 OTP Microcontroller(CMOS Z8系列一次可編程微控制器)
中文描述: 檢察官辦公室的CMOS Z8微控制器(的CMOS Z8系列一次可編程微控制器)
文件頁(yè)數(shù): 12/58頁(yè)
文件大小: 388K
代理商: Z86E34
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
12
P R E L I M I N A R Y
DS97Z8X1500
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the de-
vice. This is a stress rating only; functional operation of the
device at any condition above those indicated in the oper-
ational sections of these specifications is not implied. Ex-
posure to absolute maximum rating conditions for an ex-
tended period may affect device reliability.
Total power dissipation should not exceed 1.2 W for the
package. Power dissipation is calculated as follows:
Total Power Dissipation = V
DD
x [ I
DD
– (sum of I
OH
) ]
+ sum of [ (V
DD
– V
OH
) x I
OH
]
+ sum of (V
0L
x I
0L
)
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to
Ground. Positive current flows into the referenced pin
(Test Load).
Parameter
Min
–40
–65
–0.6
–0.3
–0.6
Max
+105
+150
+7
+7
V
DD
+1
Units
C
C
V
V
V
Ambient Temperature under Bias
Storage Temperature
Voltage on any Pin with Respect to V
SS
[Note 1]
Voltage on V
DD
Pin with Respect to V
SS
Voltage on XTAL1, P32, P33 and /RESET Pins with Respect to
V
SS
[Note 2]
Total Power Dissipation
Maximum Allowable Current out of V
SS
Maximum Allowable Current into V
DD
Maximum Allowable Current into an Input Pin [Note 3]
Maximum Allowable Current into an Open-Drain Pin [Note 4]
Maximum Allowable Output Current Sunk by Any I/O Pin
Maximum Allowable Output Current Sourced by Any I/O Pin
Maximum Allowable Output Current Sunk by /RESET Pin
1.21
220
180
+600
+600
25
25
3
W
mA
mA
μ
A
μ
A
mA
mA
mA
–600
–600
Notes:
1. This applies to all pins except XTAL pins and where otherwise noted.
2. There is no input protection diode from pin to V
DD
.
3. This excludes XTAL pins.
4. Device pin is not at an output Low state.
Figure 13. Test Load Diagram
150 pF
From Output
Under Test
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