參數(shù)資料
型號: Z86K14
廠商: ZiLOG, Inc.
英文描述: CMOS Z8 8-Bit MCU Keyboard Controllers
中文描述: Z8的CMOS 8位微控制器鍵盤控制器
文件頁數(shù): 18/24頁
文件大小: 170K
代理商: Z86K14
Z86K13/K14/K15/K16/K17/K18
CMOS Z8 8-Bit MCU Keyboard Controllers
Zilog
18
P R E L I M I N A R Y
DS97KEY0204
PIN FUNCTIONS
(Continued)
Power-On-Reset (POR).
A timer circuit is triggered by the
system oscillator and is used for the Power-On Reset
(POR) timer function. The POR time allows V
and the os-
cillator circuit to stabilize before instruction execution be-
gins. POR period is defined as:
The POR timer circuit is a one-shot timer triggered by one
of two conditions:
1.
Power fail to Power OK status
2.
Stop-Mode Recovery
The POR time is a nominal 147 ms
±
10%. At 4 MHz the
POR timer is bypassed after Stop-Mode Recovery.
HALT.
HALT turns off the internal CPU clock, but not the
RC oscillator. The counter/timer and external interrupts
IRQ0, IRQ1, IRQ2, and IRQ3 remain active. The Z86K15
is recovered by interrupts, either externally or internally
(Figure 19).
STOP.
This instruction turns off the internal clock and os-
cillator. It reduces the standby current to less than 10
μ
A.
The STOP Mode is terminated by a reset only or external
reset. This causes the processor to restart the application
program at address 000C (HEX) or the active external in-
terrupt vector. In order to enter STOP (or HALT) Mode, it
is necessary to first flush the instruction pipeline to avoid
suspending execution in mid-instruction. To do this, the
user must execute a NOP (Opcode=FFH) immediately be-
fore the appropriate sleep instruction, such as:
The Bit 6 of IRQ Registers are flags for STOP Mode Re-
covery (Figure 20).
Cold or Warm Start (D6).
This bit is set upon entering
STOP Mode. A 0 (cold) indicates that the device is awak-
ened by a POR/WDT RESET. A 1 (warm) indicates that
the device is awakened by a SMR source. This bit is reset
when read.
Negative transition on any of the designated row input pins
or host data line will recover Z86KXX from STOP Mode.
POR (ms) =
589824
f
(Hz)
FF
6F
NOP
STOP
; clear the pipeline
; enter STOP Mode
or
; clear the pipeline
; enter HALT Mode
FF
7F
NOP
HALT
Figure 19. IRQ Register
D7
D6
D5
D4
D3
D2
D1
D0
R250 IRQ
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = P30 Input
IRQ4 = TO
WDT during HALT
0 OFF *
1 ON
Stop Flag
0 POR/WDT*
1 Stop Recovery
*
On RESET
WDT Hot Bit (Read Only)
0 POR*
1 WDT Timeout
Figure 20. Stop-Mode Recovery Source
To Internal
RESET
P20-P26,
P30-P33
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