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參數(shù)資料
| 型號(hào)： | Z86L80 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | Low-Voltage Microcontroller |
| 中文描述： | 低電壓微控制器 |
| 文件頁數(shù)： | 44/58頁 |
| 文件大?。?/td> | 301K |
| 代理商： | Z86L80 |
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Z86L79/80
Low-Voltage Microcontroller
Zilog
3-44
P R E L I M I N A R Y
DS97LVO0601
FUNCTIONAL DESCRIPTION
(Continued)
SCLK/TCLK Divide-by-16 Select
(D0)
.
D0 of the SMR
controls a Divide-by-16 prescaler of SCLK/TCLK. The pur-
pose of this control is to selectively reduce device power
consumption during normal processor execution (SCLK
control) and/or HALT mode (where TCLK sources interrupt
logic). After Stop-Mode Recovery, this bit is set to a 0.
External Clock divide-by-two
(D1)
.
This bit can eliminate
the oscillator divide-by-two-circuitry. When this bit is 0, the
System Clock (SCLK) and Timer Clock (TCLK) are equal
to the external clock frequency divided-by-two. The
SCLK/TCLK is equal to the external clock frequency when
this bit is set (D1=1). Using this bit together with D7 of
PCON further helps lower EMI (i.e., D7 (PCON)=0, D1
(SMR) = 1). The default setting is zero. Maximum external
clock frequency is 4 MHz when SMR Bit D1=1 where
SCLK/TCLK=XTAL.
Note: When changing the system clock from either to
or to divide-by-two or divide-by-16, you must follow
the instruction with two NOP's in order to avoid clock
conflicts during the internal system clock frequency
change.
Stop-Mode Recovery Source
(D2, D3, and D4). These
three bits of the SMR specify the wake up source of the
STOP recovery (Figure 34 and Table 5).
Stop-Mode Recovery Delay Select
(D5). This bit, if High,
disables the 5 ms /RESET delay after Stop-Mode Recov-
ery. The default configuration of this bit is one. If the "fast"
wake up is selected, the Stop-Mode Recovery source
needs to be kept active for at least 5TpC.
Stop-Mode Recovery Edge Select
(D6). A 1 in this bit po-
sition indicates that a High level on any one of the recovery
sources wakes the Z86L7X from STOP mode. A 0 indi-
cates Low level recovery. The default is 0 on POR (Figure
36).
Cold or Warm Start
(D7). This bit is set by the device
upon entering STOP mode. A 0 in this bit (cold) indicates
that the device will be reset by POR/WDT Reset. A 1 in this
bit (warm) indicates that the device awakens by a SMR
source. This is a READ only bit.
Table 5. Stop-Mode Recovery Source
SMR: 432
D3
0
Operation
D4
0
D2
0
Description of Action
POR and/or external
reset recovery
Reserved
P31 transition
P32 transition
P33 transition
P27 transition
Logical NOR of P20
through P23
Logical NOR of P20
through P27
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
1
1
1
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