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參數(shù)資料
| 型號： | Z9972 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 3.3V, 125-MHz, Multi-Output Zero Delay Buffer |
| 中文描述： | 3.3伏，125兆赫，多輸出零延遲緩沖器 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大小： | 87K |
| 代理商： | Z9972 |
Z9972
Document #: 38-07088 Rev. *D
Page 2 of 9
Pin Descriptions
Pin
11
12
9
10
Name
XIN
XOUT
TCLK0
TCLK1
QA(3:0)
QB(3:0)
QC(3:0)
FB_OUT
PWR
I/O
I
O
I
I
O
O
O
O
Type
Description
Oscillator Input
. Connect to a crystal.
Oscillator Output
. Connect to a crystal.
External Reference/Test Clock Input
.
External Reference/Test Clock Input
.
Clock Outputs
.
See
Table 2
for frequency selections.
Clock Outputs
. See
Table 2
for frequency selections.
Clock Outputs
. See
Table 2
for frequency selections.
Feedback Clock
Output
. Connect to FB_IN for normal operation. The
divider ratio for this output is set by FB_SEL(0:2). See
Table 1
. A bypass
delay capacitor at this output will control Input Reference/ Output Banks
phase relationships.
Synchronous Pulse Output
. This output is used for system synchroni-
zation. The rising edge of the output pulse is in sync with both the rising
edges of QA (0:3) and QC(0:3) output clocks regardless of the divider
ratios selected.
Frequency Select Inputs
. These inputs select the divider ratio at QA(0:3)
outputs. See
Table 2
.
Frequency Select Inputs
. These inputs select the divider ratio at QB(0:3)
outputs. See
Table 2
.
Frequency Select Inputs
. These inputs select the divider ratio at QC(0:3)
outputs. See
Table 2
.
Feedback Select Inputs
. These inputs select the divide ratio at FB_OUT
output. See
Table 2
.
VCO Divider Select Input
. When set LOW, the VCO output is divided by
2. When set HIGH, the divider is bypassed. See
Table 1
.
Feedback Clock Input
. Connect to FB_OUT for accessing the PLL.
PLL Enable Input
. When asserted HIGH, PLL is enabled. And when
LOW, the phase-lock loop (PLL) is bypassed.
Reference Select Input
. When HIGH, the crystal oscillator is selected.
And when LOW, TCLK (0,1) is the reference clock.
TCLK Select Input
. When LOW, TCLK0 is selected and when HIGH
TCLK1 is selected.
Master Reset/Output Enable Input
. When asserted LOW, resets all of
the internal flip-flops and also disables all of the outputs. When pulled
HIGH, releases the internal flip-flops from reset and enables all of the
outputs.
Inverted Clock Input
. When set HIGH, QC(2,3) outputs are inverted.
When set LOW, the inverter is bypassed.
Serial Clock Input
. Clocks data at SDATA into the internal register.
Serial Data Input
. Input data is clocked to the internal register to
enable/disable individual outputs. This provides flexibility in power
management.
3.3V Power Supply for Output Clock Buffers
.
PU
PU
44, 46, 48, 50
32, 34, 36, 38
16, 18, 21, 23
29
VDDC
VDDC
VDDC
VDDC
25
SYNC
VDDC
O
42, 43
SELA(1,0)
I
PU
40, 41
SELB(1,0)
I
PU
19, 20
SELC(1,0)
I
PU
5, 26, 27
FB_SEL(2:0)
I
PU
52
VCO_SEL
I
PU
31
6
FB_IN
PLL_EN
I
I
PU
PU
7
REF_SEL
I
PU
8
TCLK_SEL
I
PU
2
MR#/OE
I
PU
14
INV_CLK
I
PU
3
4
SCLK
SDATA
I
I
PU
PU
17, 22, 28,
33,37, 45, 49
13
1, 15, 24, 30,
35, 39, 47, 51
VDDC
[2]
VDD
[2]
VSS
3.3V Supply for PLL
.
Common Ground
.
Note:
2.
A bypass capacitor (0.1
μ
F) should be placed as close as possible to each positive power (< 0.2
”
). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.
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