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參數(shù)資料
| 型號： | ZL10039LCG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 消費家電 |
| 英文描述： | 100A clamp for PQ meters RoHS Compliant: NA |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC28 |
| 封裝： | 5 X 5 MM, MO-220, QFN-28 |
| 文件頁數(shù)： | 11/35頁 |
| 文件大?。?/td> | 694K |
| 代理商： | ZL10039LCG |
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ZL10039
Data Sheet
11
Zarlink Semiconductor Inc.
The R[3:0] bits select the Reference Divider divide ratio. The ratio selected is not a simple binary power-of-two
value but through a lookup table, see Table 7- PLL Reference Divider Ratios.
This register controls test modes within the PLL. This should be programmed with the default settings.
2.2 RF Control Register
A single register controls RF programmability.
R3
R2
R1
R0
Division
Ratio
0
0
0
0
2
0
0
0
1
4
0
0
1
0
8
0
0
1
1
16
0
1
0
0
32
0
1
0
1
64
0
1
1
0
128
0
1
1
1
256
1
0
0
0
3
1
0
0
1
5
1
0
1
0
10
1
0
1
1
20
1
1
0
0
40
1
1
0
1
80
1
1
1
0
160
1
1
1
1
320
Table 7 - PLL Reference Divider Ratios
Bit Field
Name
Default
Type
Description
7:0
-
0X40
R/W
Test Modes
Table 8 - Register 3
Bit Field
Name
Default
Type
Description
7
-
-
R
Test Modes
6:2
-
11011
R/W
Test Modes
1
LEN
1
R/W
Bypass Enable
0
-
0
R/W
Not used
Table 9 - Register 4
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