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參數(shù)資料
| 型號： | ZL30108LDA |
| 廠商： | XILINX INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, QCC32 |
| 封裝： | 5 X 5 MM, MO-220, QFN-32 |
| 文件頁數(shù)： | 38/57頁 |
| 文件大小： | 691K |
| 代理商： | ZL30108LDA |
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ZL30108
Data Sheet
16
Zarlink Semiconductor Inc.
5.3
Reference Selection
The active reference input (REF0 or REF1) is selected by the REF_SEL pin as shown in Table 4. If the logic value
of the REF_SEL pin is changed when the DPLL is in Normal mode, the ZL30108 will perform a hitless reference
switch.
When the REF_SEL inputs are used to force a change from the currently selected reference to another reference,
the action of the LOCK output will depend on the relative frequency and phase offset of the old and new references.
Where the new reference has enough frequency offset and/or TIE-corrected phase offset to force the output
outside the phase-lock-window, the LOCK output will de-assert, the lock-qualify timer is reset, and LOCK will stay
de-asserted for the full lock-time duration. Where the new reference is close enough in frequency and TIE-
corrected phase for the output to stay within the phase-lock-window, the LOCK output will remain asserted through
the reference-switch process.
6.0
Measures of Performance
The following are some PLL performance indicators and their corresponding definitions.
6.1
Jitter Generation (Intrinsic Jitter)
Timing jitter is defined as the high frequency variation of the clock edges from their ideal positions in time. Wander
is defined as the low-frequency variation of the clock edges from their ideal positions in time. High and low
frequency variation imply phase oscillation frequencies relative to some demarcation frequency. (Often 10 Hz or
20 Hz for DS1 or E1, higher for SONET/SDH clocks.) Jitter parameters given in this data sheet are total timing jitter
numbers, not cycle-to-cycle jitter.
6.2
Jitter Tolerance
Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock in the
presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied
jitter magnitude and jitter frequency depends on the applicable standards.
6.3
Jitter Transfer
Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter
at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured
with various filters depending on the applicable standards. For the ZL30108, the internal low pass loop filter
determines the jitter attenuation.
Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for
large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter
signals (for example 75% of the specified maximum tolerable input jitter).
6.4
Frequency Accuracy
Frequency accuracy is defined as the absolute accuracy of an output clock signal when it is not locked to an
external reference, but is operating in a free running mode. For the ZL30108, the Freerun accuracy is equal to the
master clock (OSCi) accuracy.
REF_SEL
(input pin)
Input Reference Selected
0REF0
1REF1
Table 4 - Manual Reference Selection
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相關(guān)代理商/技術(shù)參數(shù) |
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| ZL30108LDE1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Network Interface DPLL |
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| ZL30109 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:DS1/E1 System Synchronizer with 19.44 MHz Output |
| ZL30109_05 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:DS1/E1 System Synchronizer with |
| ZL30109QDG | 制造商:Microsemi Corporation 功能描述: |
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