參數(shù)資料
型號(hào): ZL38002QDG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數(shù)字傳輸電路
英文描述: Low-Voltage Acoustic Echo Canceller With Noise Reduction
中文描述: DATACOM, ISDN ECHO CANCELLER, PQFP48
封裝: 7 X 7 MM, 1 MM HEIGHT, MS-026ABC, TQFP-48
文件頁(yè)數(shù): 1/47頁(yè)
文件大?。?/td> 440K
代理商: ZL38002QDG
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2005, Zarlink Semiconductor Inc. All Rights Reserved.
Features
112 ms acoustic echo canceller
Up to 12 dB of noise reduction
Works with low cost voice codec. ITU-T G.711 or
signed mag
μ
/A-Law, or linear 2’s compliment
Each port may operate independently in
companded format or linear format
Advanced NLP design - full duplex speech with
no switched loss on audio paths
Fast re-convergence time: tracks changing echo
environment quickly
Adaptation algorithm converges even during
Double-Talk
Designed for exceptional performance in high
background noise environments
Provides protection against narrow-band signal
divergence
Howling prevention stops uncontrolled oscillation
in high loop gain conditions
Programmable offset nulling of all PCM channels
Serial micro-controller interface
Idle channel noise suppression
ST-BUS, GCI, or variable-rate SSI PCM
interfaces
User gain control provided for speaker path
(-24 dB to +21 dB in 3 dB steps)
Adjustable gain pads from -24 dB to +21 dB at
Xin, Sin and Sout to compensate for different
system requirements
AGC on speaker path
Handles up to -6 dB acoustic echo return loss
(with the appropriate gain pad settings)
Transparent data transfer and mute options
20 MHz master clock operation
Low power mode during PCM Bypass
Bootloadable for future factory software upgrades
2.7 V to 3.6 V supply voltage; 5 V-tolerant inputs
August 2005
Ordering Information
ZL38002QDG
ZL38002QDG1
ZL38002DGA1
ZL38002DGB1
48 Pin TQFP
48 Pin TQFP* Trays
36 Pin QSOP* Tubes
36 Pin QSOP* Tape and Reel
* Pb Free Matte Tin
-40
°
C to 85
°
C
Trays
ZL38002
Low-Voltage Acoustic Echo Canceller
with Noise Reduction
Data Sheet
Figure 1 - Functional Block Diagram
Rout
MD1
MD2
Sin
Micro
Interface
Program
RAM
Program
ROM
Howling
Controller
NBSD
Linear/
μ
/A-Law
R
1
R
1
S
1
S
2
FORMAT
L
inear/
μ
/A-Law
HP
Filter
Linear
μ
/A-Law/
Adaptive
Filter
HP
Filter
VDD
VSS
RESET
F0i
BCLK/C4i
MCLK
Sout
Rin
DATA1
DATA2
CS
SCLK
ENA2
LAW
AGC
User
Gain
+
-
-24 -> +21dB
ADV
NLP
Linear
μ
/A-Law/
+
UNIT
CONTROL
Detector
Talk
Double
NBSD
ENA1
Limiter
Limiter
A
Gain
Pad
Gain
Pad
Gain
Pad
Noise
Reduction
相關(guān)PDF資料
PDF描述
ZL38002QDG1 Low-Voltage Acoustic Echo Canceller With Noise Reduction
ZL38002 Low-Voltage Acoustic Echo Canceller With Noise Reduction
ZL38002DGA1 Low-Voltage Acoustic Echo Canceller With Noise Reduction
ZL38002DGB1 Low-Voltage Acoustic Echo Canceller With Noise Reduction
ZL38065 32 Channel Voice Echo Canceller
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