參數(shù)資料
型號: ZL38065QCG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數(shù)字傳輸電路
英文描述: 32 Channel Voice Echo Canceller
中文描述: DATACOM, ISDN ECHO CANCELLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, MS-026BED, LQFP-100
文件頁數(shù): 38/48頁
文件大?。?/td> 658K
代理商: ZL38065QCG
ZL38065
Data Sheet
38
Zarlink Semiconductor Inc.
Power-up
00
hex
Main Control Register 0 (EC Group 0)
Page 0
A12=0
A11=0
Bit 2
Format
R/W Address:
400
hex
Bit 7
WR_all
Bit 6
ODE
Bit 5
MIRQ
Bit 4
MTDBI
Bit 3
MTDAI
Bit 1
Law
Bit 0
PWUP
Functional Description of Register Bits
Write all control bit: When high, Group 0-15 Echo Cancellers Registers are mapped into
0000
hex
to 0003F
hex
which is Group 0 address mapping. Useful to initialize the 16 Groups of
Echo Cancellers as per Group 0. When low, address mapping is per Figure 11. Note: Only the
Main Control
Register 0
has the WR_all bit.
Output Data Enable: This control bit is logically AND’d with the ODE input pin. When both ODE
bit and ODE input pin are high, the Rout and Sout outputs are enabled. When the ODE bit is
low or the ODE input pin is low, the Rout and Sout outputs are high impedance
.
Note: Only the
Main Control Register 0 has the ODE bit.
Mask Interrupt: When high, all the interrupts from the Tone Detectors output are masked. The
Tone Detectors operate as specified in their Echo Canceller B, Control Register 2.
When low, the Tone Detectors Interrupts are active.
Note: Only the Main Control Register 0 has the MIRQ bit.
Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from Echo
Canceller B is masked. The Tone Detector operates as specified in Echo Canceller B, Control
Register 2. When low, the Tone Detector B Interrupt is active.
Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from Echo
Canceller A is masked. The Tone Detector operates as specified in Echo Canceller A, Control
Register 2. When low, the Tone Detector A Interrupt is active.
ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, accept ITU-T
(G.711) PCM code. When low, both Echo Cancellers A and B for a given group, accept sign-
magnitude PCM code.
A/
μ
Law: When high, both Echo Cancellers A and B for a given group, accept A-Law
companded PCM code. When low, both Echo Cancellers A and B for a given group, accept
μ
-
Law companded PCM code.
Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given group,
are active. When low, both Echo Cancellers A and B and Tone Detectors for a given group, are
placed in Power Down mode. In this mode, the corresponding PCM data are bypassed from
Rin to Rout and from Sin to Sout with two frames delay. When the PWUP bit toggles from
zero to one, the echo canceller A and B execute their initialization routine which presets their
registers, Base Address+00
hex
to Base Address+3F
hex
, to default power up value and clears
the Adaptive Filter coefficients. Two frames are necessary for the initialization routine to
execute properly. Once the initialization routine is executed, the user can set the per channel
Control Registers for their specific application.
WR_all
ODE
MIRQ
MTDBI
MTDAI
Format
Law
PWUP
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