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ZL40518
Data Sheet
4
Zarlink Semiconductor Inc.
Small current step size Rise and Fall time will be determined by the Bandwidth of the combined network. This is
dominated by the Interconnect Inductance and the output Capacitance. Similarly, the overshoot and undershoot will
be determined by the Q of the network. This is a function of the Source Impedance from the ZL40518, the
Interconnect inductance and the Load impedance of the Laser Diode. Figure 3 includes example simplified
estimates of the Q and BW of the combined Laser Diode, ZL40518 and interconnect network for two different
interconnect inductance values (5 nH & 7 nH) and two different Diode On resistance (3 Ohm & 7 Ohm) . This
simple analysis illustrates the change in BW and Q of the network depending on these parameters. This in Turn
effects the Rise Time and Fall time and the Overshoot and Undershoot performance achieved in the application.
Specified Electrical Performance with 15 mm Interconnect and Zarlink ZLE40518 Evaluation Board
The specified performance in the table are results based on the electrical measurements and simulations across
full process corners using the Zarlink Evaluation Board using a 6.8 Ohm resistive load to ground. The track
interconnect between ZL40518 and the 6.8 Ohm Resistor is 15 mm long and uses a 2 mm wide track on single
sided FR4 board. The return path is via two 2 mm wide tracks spaced 0.25 mm either side of the track between
output and the 6.8 ohm resistor. The combined forward and return path forms a co planar transmission line with a
characteristic impedance of approximately 120 ohms. The tight coupled return paths carrying the return current
reduce the effective series inductance (Leff) which can be approximated to:-
L
eff
= 2 * Lint * (1 - K) + 2 * Lfix * (1 - K).
The ZLE40518 board has two positions for the Laser Diode at two different distances. (15 and 30 mm).
The measured value of L
eff
is 7 nH.
The estimated value of L
eff
= 2 * 8 (1 - 0.5) = 8 nH.
The actual pulse response achieved in an application is thus dependent on the application.
Application Layer Guide Lines
Minimize Interconnect Inductance by:-
a. Using Short Interconnect Distance
b. Use wide interconnect tracks
c. Keep the return path tightly coupled to the forward path