參數(shù)資料
型號: ZL50022QCC
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Enhanced 4 K Digital Switch with Stratum 4E DPLL
中文描述: TELECOM, DIGITAL TIME SWITCH, PQFP256
封裝: 28 X 28 MM, 1.40 MM HEIGHT, MS-026BJC, LQFP-256
文件頁數(shù): 57/121頁
文件大?。?/td> 939K
代理商: ZL50022QCC
ZL50022
Data Sheet
57
Zarlink Semiconductor Inc.
Bit
Name
Description
15 - 9
Unused
Reserved
In normal functional mode, these bits
MUST
be set to zero.
8
FPOF2EN
FPo_OFF2/FPo5 Enable
When this bit is high, output frame pulse FPo_OFF2/FPo5 is enabled.
When this bit is low, output frame pulse FPo_OFF2/FPo5 is in high impedance state.
7
FPOF1EN
FPo_OFF1 Enable
When this bit is high, output frame pulse FPo_OFF1 is enabled.
When this bit is low, output frame pulse FPo_OFF1 is in high impedance state.
6
FPOF0EN
FPo_OFF0 Enable
When this bit is high, output frame pulse FPo_OFF0 is enabled.
When this bit is low, output frame pulse FPo_OFF0 is in high impedance state.
5
CKO5EN
CKo5 Enable
When this bit is high, output clock CKo5 is enabled.
When this bit is low, output clock CKo5 is in high impedance state.
CKo5 is available in Master mode or in Slave mode with SLV_DPLLEN set.
4
CKO4EN
CKo4 Enable
When this bit is high, output clock CKo4 is enabled.
When this bit is low, output clock CKo4 is in high impedance state.
CKo4 is available in Master mode or in Slave mode with SLV_DPLLEN set.
3
CKOFPO3
EN
CKo3 and FPo3 Enable
When this bit is high, output clock CKo3 and output frame pulse FPo3 are enabled.
When this bit is low, CKo3 and FPo3 are in high impedance state.
2
CKOFPO2
EN
CKo2 and FPo2 Enable
When this bit is high, output clock CKo2 and output frame pulse FPo2 are enabled.
When this bit is low, CKo2 and FPo2 are in high impedance state.
1
CKOFPO1
EN
CKo1 and FPo1 Enable
When this bit is high, output clock CKo1 and output frame pulse FPo1 are enabled.
When this bit is low, CKo1 and FPo1 are in high impedance state.
0
CKOFPO0
EN
CKo0 and FPo0 Enable
When this bit is high, output clock CKo0 and output frame pulse FPo0 are enabled.
When this bit is low, CKo0 and FPo0 are in high impedance state.
Table 20 - Output Clock and Frame Pulse Control Register (OCFCR) Bits
External Read/Write Address: 0003
H
Reset Value: 0000
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
FPOF2
EN
FPOF1
EN
FPOF0
EN
CKO5
EN
CKO4
EN
CKO
FPO3
EN
CKO
FPO2
EN
CKO
FPO1
EN
CKO
FPO0
EN
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