參數(shù)資料
型號(hào): ZL50418
廠商: Zarlink Semiconductor Inc.
英文描述: Managed 16-Port 10/100 M + 2-Port 1 G Ethernet Switch
中文描述: 管理16端口10/100平方米端口1個(gè)G以太網(wǎng)交換機(jī)
文件頁(yè)數(shù): 61/163頁(yè)
文件大?。?/td> 2122K
代理商: ZL50418
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ZL50418
Data Sheet
61
Zarlink Semiconductor Inc.
When the CPU reads this register:
14.2.6 Interrupt Register
Interrupt sources (8 bits)
Address = 5 (read only)
When CPU
reads
this register
Bit [5]:
Set this bit to re-start the data that is sent from the CPU to Receive FIFO
(re-align). This feature can be used for software debug. For normal
operation must be '0'.
Bit [6]:
Do not use. Must be '0'
Bit [7]:
Reserved
Bit [0]:
Control Frame receive buffer ready, CPU can write a new frame
- 1 – CPU can write a new control command 1
- 0 – CPU has to wait until this bit is 1 to write a new control command 1
Bit [1]:
Control Frame transmit buffer1 ready for CPU to read
- 1 – CPU can read a new control command 1
- 0 – CPU has to wait until this bit is 1 to read a new control command
Bit [2]:
Control Frame transmit buffer2 ready for CPU to read
- 1 – CPU can read a new control command 1
- 0 – CPU has to wait until this bit is 1 to read a new control command
Bit [3]:
Transmit FIFO has data for CPU to read (TXFIFO_RDY)
Bit [4]:
Receive FIFO has space for incoming CPU frame (RXFIFO_SPOK)
Bit [5]:
Transmit FIFO End Of Frame (TXFIFO_EOF)
Bit [6]:
Reserve
Bit [7]:
Reserve
Bit [0]:
CPU frame interrupt
Bit [1]:
Control Frame 1 interrupt. Control Frame receive buffer1 has data for CPU
to read
Bit [2]:
Control Frame 2 interrupt. Control Frame receive buffer2 has data for CPU
to read
Bit [3]:
Gigabit port A interrupt
Bit [4]:
Gigabit port B interrupt
Bit [7:3]:
Reserve
Note:
This register is not self-cleared. After reading CPU has to clear the bit writing 0 to it.
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