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參數(shù)資料
| 型號(hào)： | ZN427E8DP |
| 元件分類(lèi)： | 參考電壓二極管 |
| 英文描述： | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
| 中文描述： | 250 的低電流運(yùn)算，低反向泄露，低噪聲穩(wěn)壓二極管 |
| 文件頁(yè)數(shù)： | 4/17頁(yè) |
| 文件大?。?/td> | 311K |
| 代理商： | ZN427E8DP |
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ZN427
3
GENERAL CIRCUIT OPERATION
The ZN427 utilises the successive approximation technique.
Upon receipt of a negative-going pulse at the
WR
input the
BUSY
output goes low, the MSB is set to 1 and all other bits
are set to 0, which produces an output voltage of V
from the
DAC. This is compared to the input voltage V
; a decision is
made on the next negative clock edge to reset the
MSB to 0 if V
IN
or leave it set to 1 if < V
IN
.
2
Bit 2 is set to 1 on the same clock edge, producing an output
V
2
from the DAC of 4
of the MSB. This voltage is compared to V
and on the next
clock edge a decision is made regarding bit 2, whilst bit 3 is set
REF
V
REF
2
V
REF
V
REF
4
to 1. This procedure is repeated for all eight bits. On the ninth
negative clock edge
BUSY
goes high indicating that the
conversion is complete.
During a conversion the RD input will normally be held high to
keep the three-state buffers in their high impedance state.
Data can be read out by taking
RD
high, thus enabling the
three-state output. Readout is non-destructive. The
BUSY
output may be tied to the RD input to automatically enable the
outputs when the data is valid.
For reliable operation of the converter the start pulse applied
to the
WR
input must meet certain timing criteria with respect
to the converter clock. These are detailed in the timing
diagram of Fig.3.
Fig.3 Timing diagram
NOTES ON TIMING DIAGRAM
1. A conversion sequence is shown for the digital word
01100110. For clarity the three-state outputs are shown as
being enabled during the conversion, but normal practice
would be to disable them until the conversion was complete.
2. The
BUSY
output goes low during a conversion. When
BUSY
goes high at the end of a conversion the output data is
valid. In a microprocessor system the
BUSY
output can be
used to generate an interrupt request when the conversion is
complete.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZN427J-8 | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
| ZN427J8DC | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
| ZN427J8 | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TVPS00; No. of Contacts:4; Connector Shell Size:21; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle; Body Style:Straight |
| ZN428 | 8-BIT LATCHED INPUT D-A CONVERTER |
| ZN428J8DC | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZN427J8 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:MICROPROCESSOR COMPATIBLE 8-BIT SUCCESSIVE APPROXIMATION A-D CONVERTER |
| ZN427J-8 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Analog-to-Digital Converter， 8-Bit |
| ZN427J8DC | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Analog-to-Digital Converter， 8-Bit |
| ZN428 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:8-BIT LATCHED INPUT D-A CONVERTER |
| ZN428D | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:8-BIT LATCHED INPUT D-A CONVERTER |
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