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參數(shù)資料
| 型號： | ZN427J-8 |
| 元件分類： | 參考電壓二極管 |
| 英文描述： | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
| 中文描述： | 250 的低電流運(yùn)算，低反向泄露，低噪聲穩(wěn)壓二極管 |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 311K |
| 代理商： | ZN427J-8 |
ZN427
4
PRACTICAL CLOCK AND SYNCHRONISING
CIRCUITS
The actual method of generating the clock signal and
synchronising it to the start conversion system in which the
ZN427 is incorporated.
When used with a microprocessor the ZN427 can be treated
as RAM and can be assigned a memory address using an
address decoder. If the
μ
P clock is used to drive the ZN427
and the
μ
P write pulse meets the ZN427 timing criteria with
respect to the
μ
P clock then generating the start pulse is
simply a matter of gating the decoded address with the
microprocessor write pulse. Whilst the conversion is being
performed the microprocesor can perform other instructions
or No operation (NOP). when the conversion is complete the
outputs can be enabled onto the bus by gating the decoded
address with the read pulse. A timing diagram for this
sequence of operation is given in Fig.4.
An advantage of using the microprocessor clock is that the
conversion time is known precisely in terms of machine
cycles. the data outputs may therefore be read after a fixed
delay of at least nine clock cycles after the end of the
WR
pulse, when the conversion will be complete.
Alternatively the read operation may be initiated by using the
BUSY
output to generate interrupt request.
3. In the timing diagram cross hatching indicates a 'don't
care' condition.
4. The start pulse operates as an asynchronous
(independent of clock) reset that sets the MSB output to 1 and
sets all other outputs and the end of conversion flag to 0. This
resetting occurs on the low-going edge of the start pulse and
as long as
WR
is low the converter is inhibited. Conversion
commences on the first active (negative going) clock edge
after the
WR
input has gone high again, when the MSB
decision is made. A number of timing constraints thus supply
to the start pulse.
(a) The minimum duration of the start pulse is 250ns, to allow
reliable resetting of the converter logic circuits.
(b) There is no limit to the maximum duration of the start pulse.
(c) To allow the MSB to settle at least 1.5
μ
s must elapse
between the negative going edge of the start pulse and the first
active clock edge that indicates the MSB desicion.
(d) To ensure relaible clocking the positive-going edge of the
start pulse should not occur within 200ns of an active
(negative-going) clock edge. The ideal place for the positive-
going edge of the start pulse is coincident with a positive-going
clock edge. As a special case of the above conditions that
start pulse may be synchronous with a negative-going clock
pulse.
Fig.4 Typical timing diagram using
μ
P clock and write pulse
In some systems, for example single-chip microcomputers
such as the 8048, this simple method may not be feasible for
one or more of the following reasons:
(a) The MPU clock is not available externally.
(b) The clock frequency is too high.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZN427J8DC | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
| ZN427J8 | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TVPS00; No. of Contacts:4; Connector Shell Size:21; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle; Body Style:Straight |
| ZN428 | 8-BIT LATCHED INPUT D-A CONVERTER |
| ZN428J8DC | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
| ZN428DMP | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZN427J8DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 8-Bit |
| ZN428 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT LATCHED INPUT D-A CONVERTER |
| ZN428D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT LATCHED INPUT D-A CONVERTER |
| ZN428DMP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Digital-to-Analog Converter |
| ZN428E8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT LATCHED INPUT D-A CONVERTER |
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