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參數(shù)資料
| 型號(hào)： | ZN428D |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8-BIT LATCHED INPUT D-A CONVERTER |
| 中文描述： | 8位DA轉(zhuǎn)換器的輸入鎖存 |
| 文件頁(yè)數(shù)： | 4/9頁(yè) |
| 文件大?。?/td> | 272K |
| 代理商： | ZN428D |
ZN428
Parameter
Min.
Typ.
Max.
Units
Conditions
Logic
(over specified operating
temperature range)
High level input voltage
2.0
-
-
V
Low level input voltage
-
-
0.8
V
High level input current
-
-
-
-
60
20
μ
μ
A
A
V
V
IN
IN
= 5.5V, V
= 2.4V, V
CC
CC
= Max.
= Max.
Low level input current
-
-
-5
μ
A
V
IN
= 0.4V, V
CC
= Max.
Input clamp diode voltage
-
-1.5
-
V
I
IN
= -8mA
Enable pulse width
100
-
-
ns
Data set-up time
150
-
-
ns
Note 4
Data hold time
10
-
-
ns
Note 5
ELECTRICAL CHARACTERISTICS
(cont.)
Note 4: Set up time before ENABLE goes high
Note 5: Hold time after ENABLE goes high
D-A CONVERTER
The converter is of the voltage switching type and uses
an R-2R ladder network as shown in Fig.3. Each 2R element
is connected to 0V or V
REF IN
by transistor voltage switches
specially designed for low offset voltage (<1mV). A binary
weighted voltage is produced at the output of the R-2R
ladder.
Fig.3 The R-2R ladder network
Analog output =
n
(V
REF IN
- V
OS
) + V
OS
256
where n is the digital input to the D-A from the data latch.
V
OS
is a small offset voltage produced by the D-A switch
currents flowing through the package lead resistance. The
value of V
removed by the setting up procedure (see Operating Notes)
and because the offset temperature coefficient is low
(
±
6
μ
V/
°
C)the effect on accuracy is negligible.
OS
is typically 1mV. This offset will normally be
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