參數(shù)資料
型號: ZPSD211R
英文描述: Field Programmable Microcontroller Peripherals(可編程邏輯,可加密,零功耗,12個可單獨配置I/O)
中文描述: 現(xiàn)場可編程微控制器外圍設備(可編程邏輯,可加密,零功耗,12個可單獨配置的I / O)
文件頁數(shù): 7/32頁
文件大?。?/td> 149K
代理商: ZPSD211R
Multiplexed Address/Data
8-bit Data Bus
Port A
I/O or low-order address lines
Port B
I/O and/or CS0–CS7
AD0/A0–AD7/A7
Low-order multiplexed address/data byte
A8–A15
High-order address bus byte
PSD211R
7
The PSD211R operates in 8-bit address/data mode, enabling it to interface directly to
8- and 16-bit microcontrollers.
Multiplexed 8-bit Address/Data Bus
The address/data bus (AD0/A0–AD7/A7) is bi-directional and permits the latching of the
address when the ALE signal is active. On the same pins, the data is read from or written to
the device; this depends on the state of the RD/E pin or PSEN pin and WR/V
PP
or R/W
pins. The high-order address bus (A8–A15) contains the high-order address bus byte. Ports
A and B can be configured as in Table 2.
A8–A15
AD0–AD7
ALE
PSEN
R/W or WR/V
PP
RD/E
A19/CSI
RESET
I/O or CS0–CS7
A16–A18 or
CS8–CS10
PA
PB
PC
I/O or A0–A7
Legend:
AD0–AD7 = Addresses A0–A7 multiplexed with data lines D0–D7.
Figure 2. Port Configurations
Operating Mode
Table 2. Bus and Port Configuration Options
Programmable
Address
Decoder (PAD)
The PSD211R consists of two programmable arrays referred to as PAD A and PAD B
(Figure 3). PAD A is used to generate chip select signals derived from the input address to
the internal EPROM blocks and I/O ports. All its I/O functions are listed in Table 3 and
shown in Figure 3. PAD B outputs to Ports B and C for off-chip usage.
PAD B can also be used to extend the decoding to select external devices or as a random
logic replacement. The input bus to both PAD A and PAD B is the same. By using the
PSDsoft Development Tools software, each programmable bit in the PAD array can have
one of three logic states of 0, 1, and don’t care (X). In a user’s logic design, both PADs can
share the same inputs, using the X for input signals that are not supposed to affect other
functions. The PADs use reprogrammable CMOS EPROM technology and can be
programmed and erased (if using windowed packages) by the user.
相關PDF資料
PDF描述
ZPSD301-15LI Field-Programmable Peripheral
ZPSD301-15LM Field-Programmable Peripheral
ZPSD301-15U Field-Programmable Peripheral
ZPSD301-90U Field-Programmable Peripheral
ZPSD301-90UI Field-Programmable Peripheral
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