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參數(shù)資料
| 型號： | SY69754ALHGTR |
| 廠商： | MICREL INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 3.3V, 622Mbps Clock and Data Recovery |
| 中文描述： | CLOCK RECOVERY CIRCUIT, PQFP32 |
| 封裝： | LEAD FREE, TQFP-32 |
| 文件頁數(shù)： | 13/14頁 |
| 文件大?。?/td> | 506K |
| 代理商： | SY69754ALHGTR |
Micrel, Inc.
SY69754AL
Appendix A
Layout and General Suggestions
November 2006
13
M9999-111406-D
hbwhelp@micrel.com
or (408) 955-1690
1. Establish controlled impedance stripline, microstrip, or
coplanar construction techniques.
2. Signal paths should have approximately the same width
as the device pads.
3. All differential paths are critical timing paths, where
skew should be matched to within ±10ps.
4. Signal trace impedance should not vary more than
±5%. If in doubt, perform TDR analysis of all high-speed
signal traces.
5. Maintain compact filter networks as close to filter pins
as possible. Provide ground plane relief under filter path
to reduce stray capacitance. Be careful of crosstalk
coupling into the filter network.
6. Maintain low jitter on the REFCLK input. Isolate the
XTAL oscillator from power supply noise by adequately
decoupling. Keep XTAL oscillator close to device, and
minimize capacitive coupling from adjacent signals.
7. Higher speed operation may require use of
fundamental-tone (third-overtone typically has more
jitter) crystal-based oscillator for optimum performance.
Evaluate and compare candidates by measuring
TXCLK jitter.
8. All unused outputs require termination. To conserve
power, unused PECL outputs can be terminated with a
1k
resistor to VEE.
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