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參數(shù)資料
| 型號： | μPD30210 |
| 廠商： | NEC Corp. |
| 英文描述： | 64-Bit MIPS RISC Microprocessor(64位MIPS RISC 微處理器) |
| 中文描述： | 64位MIPS RISC微處理器（64位的MIPS的RISC微處理器） |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 170K |
| 代理商： | ΜPD30210 |
μ
PD30200, 30210
21
Data Sheet U10116EJ6V0DS00
APPENDIX DIFFERENCES BETWEEN THE V
R
4300, V
R
4305, V
R
4310 AND V
R
4100
TM
Parameter
V
R
4300
V
R
4305
V
R
4310
V
R
4100
System bus
Write data transfer
Two buses (D/D
××
)
Four buses
(D/D
×
/D
××
/D
×××
)
Initial value setting
pins at reset time
DivMode (1:0)
(Can be set on power application only)
DivMode (2:0)
(Can be set on power
application only)
BigEndian, Div2,
HizParity
Block write access
Sequential ordering
Subblock ordering
State after final
data write
Final data retained in transfer rate setting
End of access
Non-cache
high-speed
write
Provided
Provided (Set
with a register)
CPU
Corresponding
instructions
MIPS I, II, and III instruction sets
MIPS I, II, III
instruction sets plus
sum-of-products
arithmetic
Cache memory
Data protection
None
Word parity
(instructions), byte
parity (data)
JTAG interface
Provided
None
SyncOut-SyncIn path
Provided
None
Clock interface
Input vs. internal
multiplication rate
1.5
Note 1
, 2, 3, 4
Note 2
1, 2, 3
2, 2.5
Note 3
, 3, 4,
5, 6
4
Internal vs. bus
frequency division
rate
1.5
Note 1
, 2, 3, 4
Note 2
1, 2, 3
2, 2.5
Note 3
, 3, 4,
5, 6
1, 2
Power mode
Low-power mode
Pipeline/system bus operated at a
quarter of the normal rate
Note4
None
None
Wait mode
None
Three types
PRId register
Imp = 0
×
0B
Imp = 0
×
0C
Notes
1.
The 1.5 times frequency setting is allowed with the 100 MHz model only. (With the 133 MHz model,
this setting is reserved.)
2.
The 4 times frequency setting is allowed with the 133 MHz model only. (With the 100 MHz model,
this setting is reserved.)
3.
The 2.5 times frequency setting is allowed with the 167 MHz model only. (With the 133 MHz model,
this setting is reserved.)
4.
Not supported by the 133 MHz model of the V
R
4300.
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