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參數(shù)資料
| 型號(hào)： | μPD42280 |
| 廠商： | NEC Corp. |
| 英文描述： | 2 M-Bit Field Buffer(2M位現(xiàn)場(chǎng)緩存) |
| 中文描述： | 2 m位場(chǎng)緩沖器（200萬位現(xiàn)場(chǎng)緩存） |
| 文件頁(yè)數(shù)： | 11/28頁(yè) |
| 文件大?。?/td> | 200K |
| 代理商： | ΜPD42280 |
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11
μ
PD42280
Restrictions
The
μ
PD42280 has the following restrictions. When using the
μ
PD42280, be very careful to observe these
restrictions.
(1) To read new data, the write address must precede the read address by 200 cycles or more and less than 262,224
cycles. To read old data, there must be 0 cycle difference between the write address and the read address.
(2) The
μ
PD42280 performs data transfer between the data registers and memory cell array in 64-word units.
Therefore, when a low-level WRST signal is input to an address n higher than address 80, the old data of
addresses higher than address n and up to address m indicated in the formula below is not guaranteed.
m = 143 + int
n – 80
64
64
Remark
int
n – 80
64
:
Indicates only the integral part of the result of n – 80 divided by 64.
Example: If n = 280
→
3
Therefore, m = 335 and old data from address 280 to address 335 is not guaranteed.
This restriction applies to internal operation during write reset. When write reset is executed by inputting a low
level to WRST, the contents of the write data register at that moment are transferred to DRAM cells.
Figure 4 -1 shows the data transmission from the write data register to DRAM chronologically. Data transfer from
the write data register to DRAM is performed in units of 64 words.
Figure 4-1 Data Transfer During Write Reset
B
64 words
64 words
Write reset
Write address
Transfer to
DRAM cells
Transfer to
DRAM cells
This range of data is
transferred to DRAM cells
A
In Figure 4-1, when write reset is applied at point A, the data after point A up to point B is also transferred to
DRAM. In other words, the old data stored in the transfer destination of this portion of data is overwritten by this
portion of data.
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