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CHAPTER 8 SERIAL INTERFACE FUNCTION
(2) Enabling transmission/reception
The CSIn of the V853 has only one 8-bit shift register and does not have a buffer. Transmission and reception
are therefore performed simultaneously.
(a) Transmission/reception enabling condition
CTXEn and CRXEn bits of CSIMn register specify the condition of CSIn transmission/reception enable.
The following conditions must be set beforehand:
ASIM00 register TXE0 bit = RXE0 bit = 0 in CSI0
ASIM10 register TXE1 bit = RXE1 bit = 0 in CSI1
CTXEn
CRXEn
Transmission/reception operation
0
0
Transmission/reception disable
0
1
Reception enable
1
0
Transmission enable
1
1
Transmission/reception enable
Remark
n = 0 to 3
(i)
Disabling SIOn output by CTXEn bit
When CTXEn bit = 0, CSIn is as follows.
CSI0, CSI1: The serial output becomes high impedance or UARTn output.
CSI2, CSI3: The serial output becomes high impedance.
When CTXEn = 1, the data of the shift register is output.
(ii) Disabling SIOn input by CRXEn bit
When CRXEn bit = 0, the shift register input is “0”.
When CRXEn bit = 1, the serial input data is input to the shift register.
(iii) To check transmit data
To receive the transmit data and to check whether bus contention occurs, set CTXEn bit and CRXEn
bit to 1.
(b) Starting transmission/reception
Transmission/reception is started by reading/writing the SIOn registers. Transmission/reception is
controlled by setting the transmission enable bit (CTXEn) and reception enable bit (CRXEn) as follows:
CTXEn
CRXEn
Start Condition
0
0
Does not start
0
1
Reads SIOn registers
1
0
Writes SIOn registers
1
1
Writes SIOn registers
0
0 -> 1
Rewrites CRXEn bits
In the above table, note that these bits should be set in advance of data transfer. For example,
if the CTXEn bit is not changed from 0 to 1 before reading data from or writing data to the SIOn registers,
transfer will not begin. The bottom of the table means that, if the CRXEn bit is changed from 0 to 1
when the CTXEn bit is “0”, the serial clock will be generated to initiate receive operation.