
287
APPENDIX B INSTRUCTION SET LIST
Instruction Set (alphabetical order) (2/4)
i
r
l
CY OV S
Z
SAT
LDSR
reg2, regID
SR[regID]<-GR[reg2] regID = EIPC, FEPC
1
1
3
regID = EIPSW, FEPSW
1
regID = PSW
1
x
x
x
x
x
MOV
reg1, reg2
GR[reg2]<-GR[reg1]
1
1
1
imm5, reg2
GR[reg2]<-sign-extend(imm5)
1
1
1
MOVEA
imm16, reg1, reg2
GR[reg2]<-GR[reg1]+sign-extend(imm16)
1
1
1
MOVHI
imm16, reg1, reg2
GR[reg2]<-GR[reg1]+(imm16 || 0
16
)
1
1
1
MULH
reg1, reg2
GR[reg2]<-GR[reg2]
Note 2
xGR[reg1]
Note 2
1
1
2
(Signed multiplication)
imm5, reg2
GR[reg2]<-GR[reg2]
Note 2
xsign-extend(imm5)
1
1
2
(Signed multiplication)
MULHI
imm16, reg1, reg2
GR[reg2]<-GR[reg1]
Note 2
ximm16
1
1
2
(Signed multiplication)
NOP
Uses 1 clock cycle without doing anything
1
1
1
NOT
reg1, reg2
GR[reg2]<-NOT(GR[reg1])
1
1
1
0
x
x
NOT1
bit#3, disp16[reg1]
adr<-GR[reg1]+sign-extend(disp16)
4
4
4
x
Z flag<-Not(Load-memory-bit(adr, bit#3))
Store-memory-bit(adr, bit#3, Z flag)
OR
reg1, reg2
GR[reg2]<-GR[reg2]OR GR[reg1]
1
1
1
0
x
x
ORI
imm16, reg1, reg2
GR[reg2]<-GR[reg1]OR zero-extend(imm16)
1
1
1
0
x
x
RETI
if PSW.EP=1
4
4
4
R
R
R
R
R
then PC
<-EIPC
PSW <-EIPSW
else if PSW.NP=1
then PC
<-FEPC
PSW <-FEPSW
else PC
<-EIPC
PSW <-EIPSW
SAR
reg1, reg2
GR[reg2]<-GR[reg2]arithmetically shift right
1
1
1
x
0
x
x
by GR[reg1]
imm5, reg2
GR[reg2]<-GR[reg2]arithmetically shift right
1
1
1
x
0
x
x
by zero-extend(imm5)
Notes
1.
The op code of this instruction uses the field of reg1 though the source register is shown as reg2 in
the above table. Therefore, the meaning of register specification for mnemonic description and op
code is different from that of the other instructions.
rrrrr = regID specification
RRRRR = reg2 specification
2.
Only the lower half-word data is valid.
Operation
Operand
Op Code
r r r r r 111111RRRRR
0000000000100000
Note 1
r r r r r 000000RRRRR
r r r r r 010000 i i i i i
r r r r r 110001RRRRR
i i i i i i i i i i i i i i i i
r r r r r 110010RRRRR
i i i i i i i i i i i i i i i i
r r r r r 000111RRRRR
r r r r r 010111 i i i i i
r r r r r 110111RRRRR
i i i i i i i i i i i i i i i i
0000000000000000
r r r r r 000001RRRRR
01bbb111110RRRRR
dddddddddddddddd
r r r r r 001000RRRRR
r r r r r 110100RRRRR
i i i i i i i i i i i i i i i i
0000011111100000
0000000101000000
r r r r r 111111RRRRR
0000000010100000
r r r r r 010101 i i i i i
Mnemonic
Execution
Clock
Flag