參數(shù)資料
型號: μPD750106
廠商: NEC Corp.
英文描述: 4 Bit Single Chip Microcontrollers(4位單片微控制器)
中文描述: 4位單片微控制器(4位單片微控制器)
文件頁數(shù): 59/80頁
文件大小: 352K
代理商: ΜPD750106
59
m
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
SCK cycle time
SCK high/low level
width
SI
Note 1
setup time
(referred to SCK
)
SI
Note 1
hold time
(referred to SCK
)
Delay time from SCK
to SO
Note 1
output
SERIAL TRANSFER OPERATION
Two-wire and three-wire serial I/O modes (SCK: Internal clock output): (T
A
= -40 to +85 °C, V
DD
= 1.8 to 5.5 V)
Notes 1.
In two-wire serial I/O mode, SO should be read as SB0 or SB1.
2.
R
L
is the resistance of the SO output line load, while C
L
is the capacitance.
Two-wire and three-wire serial I/O modes (SCK: External clock input): (T
A
= -40 to +85 °C, V
DD
= 1.8 to 5.5 V)
Notes 1.
In two-wire serial I/O mode, SO should be read as SB0 or SB1.
2.
R
L
is the resistance of the SO output line load, while C
L
is the capacitance.
TYP.
MAX.
300
1,000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN.
800
3,200
400
1,600
100
150
400
600
0
0
Conditions
V
DD
= 2.7 to 5.5 V
V
DD
= 2.7 to 5.5 V
V
DD
= 2.7 to 5.5 V
V
DD
= 2.7 to 5.5 V
R
L
= 1 ky
Note 2
C
L
= 100 pF
V
DD
= 2.7 to 5.5 V
Symbol
t
KCY2
t
KL2
,
t
KH2
t
SIK2
t
KSI2
t
KSO2
Parameter
SCK cycle time
SCK high/low level
width
SI
Note 1
setup time
(referred to SCK
)
SI
Note 1
hold time
(referred to SCK
)
Delay time from SCK
to SO
Note 1
output
MIN.
1,300
3,800
t
KCY1
/2 - 50
t
KCY1
/2 - 150
150
500
400
600
0
0
Conditions
V
DD
= 2.7 to 5.5 V
V
DD
= 2.7 to 5.5 V
V
DD
= 2.7 to 5.5 V
V
DD
= 2.7 to 5.5 V
R
L
= 1 ky
Note 2
C
L
= 100 pF
V
DD
= 2.7 to 5.5 V
Symbol
t
KCY1
t
KL1
,
t
KH1
t
SIK1
t
KSI1
t
KSO1
TYP.
MAX.
250
1,000
相關PDF資料
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μPD750106(A) 4 Bit Single Chip Microcontrollers(4位單片微控制器)
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μPD750104 4Bit Single Chip Microcontrollers(4 位微控制器)
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