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CHAPTER 18 SERIAL INTERFACE (IIC0) (
μ
PD780024Y, 780034Y SUBSERIES ONLY)
(2) IIC status register (IICS0)
This register indicates the status of the I
2
C.
IICS0 can be set by a 1-bit or 8-bit memory manipulation instruction. IICS0n is a read-only register.
RESET input sets the value to 00H.
Figure 18-4. IIC Status Register Format (IICS0) (1/3)
Address: FFA9H After reset: 00H R
Symbol
7
6
5
4
3
2
1
0
IICS0
MSTS0
ALD0
EXC0
COI0
TRC0
ACKD0
STD0
SPD0
MSTS0
Master device status
0
Slave device status or communication standby status
1
Master device communication status
Condition for clearing (MSTS0 = 0)
Condition for setting (MSTS0 = 1)
When a stop condition is detected
When ALD0 = 1
Cleared by LREL0 = 1
When IICE0 changes from 1 to 0
When RESET is input
When a start condition is generated
ALD0
Detection of arbitration loss
0
This status means either that there was no arbitration or that the arbitration result was a “win”.
1
This status indicates the arbitration result was a “l(fā)oss”. MSTS0 is cleared.
Condition for clearing (ALD0 = 0)
Condition for setting (ALD0 = 1)
Automatically cleared after IICS0 is read
Note
When IICE0 changes from 1 to 0
When RESET is input
When the arbitration result is a “l(fā)oss”.
EXC0
Detection of extension code reception
0
Extension code was not received.
1
Extension code was received.
Condition for clearing (EXC0 = 0)
Condition for setting (EXC0 = 1)
When a start condition is detected
When a stop condition is detected
Cleared by LREL0 = 1
When IICE0 changes from 1 to 0
When RESET is input
When the high-order four bits of the received
address data is either “0000” or “1111”
(set at the rising edge of the eighth clock).
Note
This register is also cleared when a bit manipulation instruction is executed for bits other than IICS0.