440
APPENDIX E REVISION HISTORY
(2/3)
Edition No.
Main revised contents from old edition
Revised Sections
2nd edition
The following two items removed from External Interrupt
Detect T100/P70/TO0 Pin Input Edge
Detect T101/P71 Pin Input Edge
Data Hold Voltage at STOP Mode Changed
1.8 V
→
1.6 V
A/D Converter in HALT Mode Operating Statuses Revised
Operation enable
→
Operation halt
Clock Output/Buzzer Output Control Circuit in STOP Mode Operating Status
added
DF780024 added to Device File
The product name of Flash Programmer changed
Flashpro
→
Flashpro II (Cavity No. FL-PR2)
The product name of Flash Memory Writing Adapter changed
PA-FLASH64CW
→
FA-64CW, PA-FLASH64GC
→
FA-64GC,
PA-FLASH64GK
→
FA-64GK
The product name of In-Circuit Emulator changed
IE-780000-SL
→
IE-78001-R-A
CPU Core Board(IE-78K0-SL-EM) removed
The product name of Conversion Socket changed
EV-9200GC-64
→
TGC-064SAP
Former edition, development Environment When Using IE-78000-R-A
removed
3rd edition
Caution about A/D Conversion Result Register (ADCR0) read operation added.
Caution about setting of port mode register and output latch is added.
Description of LREL0 flag of IIC Control Register (IICC0) revised.
Communication reservation check method changed.
Description revised: In-circuit emulator IE-78K0-NS is supported.
Description revised: Fuzzy inference development support system is deleted.
CHAPTER 19 INTER-
RUPT FUNCTIONS
CHAPTER 21
STANDBY FUNCTIONS
APPENDIX B DEVEL-
OPMENT TOOLS
CHAPTER 13 8-BIT A/D
CONVERTER
(
μ
PD780024, 780024Y
SUBSERIES),
CHAPTER 14 10-BIT A/D
CONVERTER
(
μ
PD780034, 780034Y
SUBSERIES)
CHAPTER 16 SERIAL
INTERFACE (UART0),
CHAPTER 17 SERIAL
INTERFACE (SIO3),
CHAPTER 18 SERIAL
INTERFACE (IIC0)
(
μ
PD780024Y, 780034Y
SUBSERIES ONLY)
CHAPTER 18 SERIAL
INTERFACE (IIC0)
(
μ
PD780024, 780024Y
SUBSERIES ONLY)
APPENDIX B DEVEL-
OPMENT TOOLS
APPENDIX C EMBED-
DED SOFTWARE