1
C
Figure 7-1. Block Diagram of Clock Generation Circuit
Subsystem
clock
oscillation
circuit
Main system
clock
oscillation
circuit
X2
X1
f
XT
XT2
XT1/P04
FRC
STOP
MCC
FRC
CLS
CSS
PCC2
PCC1
PCC0
Internal bus
Standby
control
circuit
To INTP0
sampling clock
S
2
f
X
2
2
f
X
2
3
f
X
2
4
f
X
Prescaler
Clock to peripheral
hardware
3
Prescaler
Processor clock control register
Watch timer, clock output function
f
X
CPU clock
Wait
control
circuit