481
CHAPTER 24 INSTRUCTION SET
Clock
Flag
Note 1
Note 2
Z AC CY
XCH
A, r
Note 3
1
4
–
A
r
A, saddr
2
8
12
A
(saddr)
A, sfr
2
–
12
A
sfr
A, !addr16
3
16
20 + 2n + 2m
A
(addr16)
A, [DE]
1
8
12 + 2n + 2m
A
(DE)
A, [HL]
1
8
12 + 2n + 2m
A
(HL)
A, [HL + byte]
2
16
20 + 2n + 2m
A
(HL + byte)
A, [HL + B]
2
16
20 + 2n + 2m
A
(HL + B)
A, [HL + C]
2
16
20 + 2n + 2m
A
(HL + C)
MOVW
rp, #word
3
12
–
rp
←
word
saddrp, #word
4
16
20
(saddrp)
←
word
sfrp, #word
4
–
20
sfrp
←
word
AX, saddrp
2
12
16
AX
←
(saddrp)
saddrp, AX
2
12
16
(saddrp)
←
AX
AX, sfrp
2
–
16
AX
←
sfrp
sfrp, AX
2
–
16
sfrp
←
AX
AX, rp
Note 4
1
8
–
AX
←
rp
rp, AX
Note 4
1
8
–
rp
←
AX
AX, !addr16
3
20
24 + 4n AX
←
(addr16)
!addr16, AX
3
20
24 + 4m (addr16)
←
AX
XCHW
AX, rp
Note 4
1
8
–
AX
rp
ADD
A, #byte
2
8
–
A, CY
←
A + byte
×
×
×
saddr, #byte
3
12
16
(saddr), CY
←
(saddr) + byte
×
×
×
A, r
Note 3
2
8
–
A, CY
←
A + r
×
×
×
r, A
2
8
–
r, CY
←
r + A
×
×
×
A, saddr
2
8
10
A, CY
←
A + (saddr)
×
×
×
A, !addr16
3
16
18 + 2n A, CY
←
A + (saddr16)
×
×
×
A, [HL]
1
8
10 + 2n A, CY
←
A + (HL)
×
×
×
A, [HL + byte]
2
16
18 + 2n A, CY
←
A + (HL + byte)
×
×
×
A, [HL + B]
2
16
18 + 2n A, CY
←
A + (HL + B)
×
×
×
A, [HL + C]
2
16
18 + 2n A, CY
←
A + (HL + C)
×
×
×
Notes 1.
When the internal high-speed RAM area is accessed or when an instruction that does not access data
is executed
2.
When an area other than the internal high-speed RAM area is accessed
3.
Except r = A
4.
Only when rp = BC, DE, HL
Remarks 1.
One clock of an instruction is equal to one CPU clock (f
CPU
) selected by processor clock control
register (PCC).
2.
The number of clocks shown is when the program is stored in the internal ROM area.
3.
n indicates the number of wait states when the external memory extension area is read.
4.
m indicates the number of wait states when the external memory extension area is written.
Mnemonic
Operand
Byte
Operation
8-bit data
transfer
Instruction
Group
16-bit
data
transfer
8-bit
operation