
CHAPTER 14 SERIAL INTERFACE CHANNEL 0
212
R/W
Use for bus release signal output.
When RELT = 1, SO latch is set to 1. After SO latch setting, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
RELT
R/W
Use for command signal output.
When CMDT = 1, SO latch is cleared to (0). After SO latch clearance, automatically cleared to (0).
Also cleared to (0) when CSIE0 = 0.
CMDT
R
RELD
Bus Release Detection
Clear Conditions (RELD = 0)
Set Conditions (RELD = 1)
When transfer start instruction is executed
If SIO0 and SVA values do not match in address
reception
When CSIE0 = 0
When RESET input is applied
When bus release signal (REL) is detected
R
CMDD
Command Detection
Clear Conditions (CMDD = 0)
Set Conditions (CMDD = 1)
When transfer start instruction is executed
When bus release signal (REL) is detected
When CSIE0 = 0
When RESET input is applied
When command signal (CMD) is detected
R/W
Acknowledge signal is output in synchronization with the falling edge clock of SCK0 just after execu-
tion of the instruction to be set to 1, and after acknowledge signal output, automatically cleared to 0.
Used as ACKE = 0. Also cleared to 0 upon start of serial interface transfer or when CSIE0 = 0.
ACKT
(continued)
Note
Bits 2, 3 and 6 (RELD, CMDD and ACKD) are Read-Only bits.
Remarks 1.
Bits 0, 1, and 4 (RELT, CMDT, and ACKT) are 0 when read after data setting.
2.
CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
(b) Serial bus interface control register (SBIC)
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SBIC to 00H.
6
5
4
3
2
1
0
7
Symbol
SBIC
BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
FF61H 00H R/W
Note
Address After Reset R/W