CHAPTER 14 SERIAL INTERFACE CHANNEL 0
229
(a) Serial operating mode register 0 (CSIM0)
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM0 to 00H.
R/W
CSIM CSIM
01
0
Serial Interface Channel 0 Clock Selection
00
×
Input clock to SCK0 pin from off-chip
1
0
8-bit timer register 2 (TM2) output
1
1
Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
R/W
CSIM CSIM CSIM
PM25
04
03
P25
PM26
P26
PM27
P27
Operating
Mode
Start
Bit
SI0/P25
Pin Function
SO0/P26
Pin Function
SCK0/P27
Pin Function
02
0
×
3-wire serial I/O mode (Refer to
14.4.2 3-wire serial I/O mode operation
)
1
0
SBI mode (Refer to
14.4.3 SBI mode operation
)
Note 2
×
Note 2
×
P25
(CMOS
input/output)
SB1/P26
(N-ch open-drain
input/output)
0
0
0
0
1
2-wire serial
I/O mode
SCK0
1
1
MSB
(N-ch open-drain
input/output)
Note 2
Note 2
SB0
P26
1
0
0
0
1
(N-ch open-drain
input/output)
(CMOS input/
output)
R/W WUP
Wake-up Function Control
Note 3
0
Interrupt request signal generation with each serial transfer in any mode
1
Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1) matches the
slave address register in SBI mode
R
COI
Slave Address Comparison Result Flag
Note 4
0
Slave address register not equal to serial I/O shift register 0 data
1
Slave address register equal to serial I/O shift register 0 data
R/W
CSIE0
Serial Interface Channel 0 Operation Control
0
Operation stopped
1
Operation enable
Notes 1.
Bit 6 (COI) is a Read-Only bit.
2.
Can be used freely as port function.
3.
Be sure to set WUP to 0 when the 2-wire serial I/O mode.
4.
When CSIE0 = 0, COI becomes 0.
Remark
×
: don’t care
PMxx: Port mode register
Pxx: Port output latch
CSIE0
COI WUPC04
CSIM
03
CSIM
02
CSIM
01
CSIM
00
7
6
5
4
3
2
1
0
CSIM0
Symbol
FF60H 00H R/W
Note 1
Address After Reset R/W