參數(shù)資料
型號(hào): μPD78063Y
廠商: NEC Corp.
英文描述: 8 Bit Single Chip Microcontrollers(8位單片微控制器)
中文描述: 8位單片機(jī)微控制器(8位單片微控制器)
文件頁(yè)數(shù): 46/68頁(yè)
文件大?。?/td> 444K
代理商: ΜPD78063Y
46
m
m
PD78062Y, 78063Y, 78064Y
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
V
DD
= 2.7 to 6.0 V
1600
3200
650
1300
800
1600
ns
ns
ns
ns
ns
ns
V
DD
= 2.7 to 6.0 V
V
DD
= 2.7 to 6.0 V
100
ns
t
KCY4
/2
ns
R = 1 k
W
,
C = 100 pF
Note
V
DD
= 4.5 to 6.0 V
0
0
300
500
ns
ns
1000
ns
(iii) 2-wire serial I/O mode (SCK0... Internal clock output)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
V
DD
= 2.7 to 6.0 V
1600
3200
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
DD
= 2.7 to 6.0 V
t
KCY3
/2–160
t
KCY3
/2–190
t
KCY3
/2–50
t
KCY3
/2–100
300
350
400
V
DD
= 4.5 to 6.0 V
4.5 V
V
DD
6.0 V
2.7 V
V
DD
< 4.5 V
600
ns
0
300
ns
t
KCY3
t
KSI3
t
KSO3
t
SIK3
t
KH3
t
KL3
R = 1 k
W
,
C = 100 pF
Note
t
KCY4
t
KH4
t
KL4
t
SIK4
t
KSI4
t
KSO4
(iv) 2-wire serial I/O mode (SCK0... External clock input)
SCK0 cycle time
SCK0 high-level width
SCK0 low-level width
SB0, SB1 setup time
(to SCK0
)
SB0, SB1 hold time
(from SCK0
)
SB0, SB1 output delay
time from SCK0
Note
R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output line.
Note
R and C are the load resistance and load capacitance of the SB0 and SB1 output line.
SCK0 cycle time
SCK0 high-level width
SCK0 low-level width
SB0, SB1 setup time
(to SCK0
)
SB0, SB1 hold time
(from SCK0
)
SB0, SB1 output delay
time from SCK0
SCK0 rise, fall time
t
R4
,
t
F4
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