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| 型號(hào)： | μPD78078Y |
| 廠商： | NEC Corp. |
| 元件分類(lèi)： | 8位微控制器 |
| 英文描述： | 8 Bit Single Chip Microcontrollers |
| 中文描述： | 8位單片機(jī)微控制器 |
| 文件頁(yè)數(shù)： | 30/84頁(yè) |
| 文件大?。?/td> | 625K |
| 代理商： | ΜPD78078Y |
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30
μ
PD78076Y, 78078Y
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS
6.1 Interrupt Functions
A total of 24 interrupt sources are provided, divided into the following three types.
Non-maskable interrupt
: 1
Maskable interrupt
: 22
Software interrupt
: 1
Table 6-1. List of Interrupt Sources
Interrupt
Type
Default
Priority
Interrupt Source
Internal/
External
Vector
Table
Address
Basic
Configuration
Type
Name
Trigger
Non-
maskable
—
INTWDT
Overflow of watchdog timer (When the watchdog
timer mode 1 is selected)
Internal
0004H
(A)
Maskable
0
INTWDT
Overflow of watchdog timer (When the interval
timer mode is selected)
(B)
1
INTP0
Pin input edge detection
External
0006H
(C)
2
INTP1
0008H
(D)
3
INTP2
000AH
4
INTP3
000CH
5
INTP4
000EH
6
INTP5
0010H
7
INTP6
0012H
8
INTCSI0
Completion of serial interface channel 0 transfer
Internal
0014H
(B)
9
INTCSI1
Completion of serial interface channel 1 transfer
0016H
10
INTSER
Occurrence of serial interface channel 2 UART
reception error
0018H
11
INTSR
INTCSI2
Completion of serial interface channel 2 UART reception
Completion of serial interface channel 2 3-wire transfer
001AH
12
INTST
Completion of serial interface channel 2 UART
transmission
001CH
13
INTTM3
Reference interval signal from watch timer
001EH
14
INTTM00
Generation of matching signal of 16-bit timer register
and capture/compare register (CR00)
0020H
15
INTTM01
Generation of matching signal of 16-bit timer register
and capture/compare register (CR01)
0022H
16
INTTM1
Generation of matching signal of 8-bit timer/event
counter 1
0024H
17
INTTM2
Generation of matching signal of 8-bit timer/event
counter 2
0026H
18
INTAD
Completion of A/D conversion
0028H
19
INTTM5
Generation of matching signal of 8-bit timer/event
counter 5
002AH
20
INTTM6
Generation of matching signal of 8-bit timer/event
counter 6
Execution of BRK instruction
002CH
Software
—
BRK
—
003EH
(E)
Notes 1.
Default priority is the priority order when several maskable interrupt requests are generated at the
same time. 0 is the highest order and 20 is the lowest order.
2.
Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1.
Note 1
Note 2
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